Low power dual edge triggered flip-flop

Saini, N.; Kashyap, Kamal Kant

doi:10.1109/icspct.2014.6885022

Cited by 8 publications

(5 citation statements)

References 10 publications

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“…Complementary clock power division of the system thanks to new generation frequency scaling and extensive pipelining. Due to the power consumption constraints of today's portable digital circuits, it is necessary to reduce the power consumption of clock networks and flip-flops [2].…”

Section: Low Power Designmentioning

confidence: 99%

“…Double-edge triggering refers to capturing data on both the rising and falling edges of each clock cycle, resulting in two data captures within one clock period. Given the substantial power dissipation stemming from clock lines, a novel low-power pulse generation circuit has been proposed [2]. This circuit, tailored for the 45nm technology node, employs signal propagation from input sources to internal nodes of latches.…”

Section: Double-edge Triggeringmentioning

confidence: 99%

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Advancements In Low-Power Technologies: Clock-Gated Circuits and Beyond

Hu,

Hou,

Lin

2024

HSET

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With the continuous advancement of the integrated circuit industry, there has been a steady rise in the level of integration and circuit scale. This inevitably leads to an escalation in power consumption by electronic devices, underscoring the growing significance of low-power technology. This comprehensive review initiates by elucidating the fundamental concept of low power, followed by an exploration of optimization measures utilizing clock-gated circuits as a prime example. Subsequently, it outlines the current challenges and prospects associated with low-power technologies. The core focus of this review revolves around the utilization of clock tree structures and triggers, which constitute the primary contributors to dynamic power consumption. These methodologies are presently the most prevalent and efficacious means to curtail power consumption through clock gating. The methodologies expounded in this review adeptly fulfill the objective of power reduction, ensuring that both present and future integrated circuits remain highly efficient. Thus, underscoring the critical role of low-power design in the realm of integrated circuit design.

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Section: Low Power Designmentioning

confidence: 99%

Section: Double-edge Triggeringmentioning

confidence: 99%

Advancements In Low-Power Technologies: Clock-Gated Circuits and Beyond

Hu,

Hou,

Lin

2024

HSET

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“…It consist of 20 transistors out of which 10 transistors form 2 latches remaining 10 transistors used for clocking. The only disadvantage in this technique is its transistor count when used for ultra large scale IC designs [29][30][31]. Because of increasingly number of switching transistors DETFF1 demonstrates progressively unique power scattering at higher frequencies despite the fact that it replaces ordinary master slave flip-flops [31].…”

Section: Existing Techniquesmentioning

confidence: 99%

“…Quadratic decline in energy consumption can be attained by scaling down supply voltage. Therefore, voltage scaling is widely adopted between IoT applications where power consumption is major constraint [30]. and battery-operated miniature sensor.…”

Section: Introductionmentioning

confidence: 99%

High Speed High Capacity Memories for Secured Internet of Things based systems

2020

IJATCSE

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The Internet of Things (IoT) is a network connecting objects ranging from remote sensors to smart devices and tablets. To support high speed and high caacity networking speed the database management system (DBMS). To meet the requirements of DBMS of IoT smart micro devices are in high demand to store and access the data. Dual Edge Triggering (DET) flip-flops stand out to be a unique solution overcoming the trade-offs between speed and power. This paper presents a 64-bit register to control the flow of data to enhance the communication between devices connected over IoT. Though the concept of DET is subsisting, the design of area power and delay flipflops efficient is still under design process. In this paper two new D-type flip-flops with Dual Edge Triggering are proposed. One among the two consists of 14 Transistors (14T) and the other consists of 12 Transistors (12T). The two designs are compared with existing 16 Transistor (16T) DET Flip-Flop. 14T DETFF (Dual Edge Triggered Flip-Flop) is found to be efficient in terms of area power and delay parameters. 12T DETFF shows really amazing and efficient results than 14T. Results are derived by simulating the circuits at 45nm technology at 1.2V supply voltage. It is observed that propagation delay of 14T is reduced by 45.39% when compared with 16T, for 12T it is reduced by 60.52% with respect to 16T. For 14T decrease in area is observed to be 18.42%, and 12T 36.16% of area is reduced when compared with 16T. Examinations of Dynamic Power scattering is finished with various capacitive loads, at various frequencies for multi bit registers extended up to 64-bits.

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“…Flip-Flops are critical timing elements in digital circuits & have a large impact on circuit speed & power consumption. Consequently, extensive has been performed to develop fast & low flops [1][2][3][4][5] The primary measure of performance of a flip-flop is the minimum Dto about the speed of operations of the flip cycle time. Recently, pulsed latc emerged as the fastest known flip [2].…”

mentioning

confidence: 99%

Design of Dual Pulsating Latch Flip-Flop DPLFF using Novel Pulse Generator

Vishwakarma¹,

Kapse²

2018

IJTSRD

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In this paper various flip-flop structures have been studied. In all designs to reduce power consumption, the Pulse Generator circuitry should be in build along with the flip-flop itself. If a pulse generator is included along with DPSCRFF structure, power consumption can be reduced. In this work a new design of flip-flop, Double Pulse Latch Flip (DPLFF) is proposed. DPLFF eliminates unnecessary glitches, which consume more power. DPLFF consume less power for same delay as compared with other existing techniques, which is performing one of the fastest known flip-flops. In serial operation as shift register the proposed DPLFF can perform better at the higher frequency. The stacking of transistor in the latch stage cause reduction in subthr leakage current & thus the static power consumption is also less for DPLFF. This is better suited for low power circuits at deep submicron technology where leakages are more dominant.

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Low power dual edge triggered flip-flop

Cited by 8 publications

References 10 publications

Advancements In Low-Power Technologies: Clock-Gated Circuits and Beyond

Advancements In Low-Power Technologies: Clock-Gated Circuits and Beyond

High Speed High Capacity Memories for Secured Internet of Things based systems

Design of Dual Pulsating Latch Flip-Flop DPLFF using Novel Pulse Generator

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