Low Power Dynamic Buffer Circuits

Abstract

In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18µm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing standard domino circuit for different logic function, loading condition, clock frequency, temperature and power supply. Our proposed circuits reduce power consumption and power delay product as compared to standard domino circuit.

Sleep signal controlled footless domino circuit for low leakage current

“…These circuits require less area and reduce the output load capacitance. This results in significant speed enhancement of the domino circuits (Pandey et al, 2012a(Pandey et al, , 2012b. The scaling of CMOS technology is required to reduce the area and to yield steady output.…”

CRDOM : Cell Re-Ordering Based Domino On-The-Fly Mapping

“…Of late, Domino logic style is employed in designing various high performance circuits [1], [2], [3], [4], [5], [6], [7], [8]. Traditionally technology mapping procedures rely on predefined standard cell libraries [9], [10], [11], [12].…”

Static Switching Dynamic Buffer Circuit

“…Buffer is essential to drive the output of domino circuit into the next stage [6,7]. Static CMOS logic circuit consumes power during the toggling of the output state.…”