Low power dynamic circuit for power efficient bit lines

Asyaei, Mohammad; Ebrahimi, Ebrahim

doi:10.1016/j.aeue.2017.08.048

Cited by 21 publications

(5 citation statements)

References 14 publications

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“…The amount of power required by a circuit when all of its inputs are set to zero is known as stand-by power [21,[24][25][26][27][28][29].…”

Section: Standby Powermentioning

confidence: 99%

The assessment of Noise Immunity in Domino Employing Silicon Nano Materials

Garg,

Gupta,

Pandey

et al. 2023

Preprint

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This article describes a novel Low Voltage Noise Immune Domino Logic (LVNIDL), which can be used to create CMOS domino using Si Nanomaterials. In 32 nm nano size silicon CMOS technology, wide fan-in input domino OR gate have been proposed and have already undergone HSPICE simulation. For the transient analysis of domino gates in the simulation, a D.C supply voltage of 0.9V and a frequency of 100 MHz are utilised. The proposed technique consumes 76.07% less power than the preceding conditional stacked keeper domino logic. Furthermore, when compared to the existing CPVT technique, the designed LVNIDL technique reduces maximum delay by 56.25%. The LVNIDL technique boosts the power delay product by up to 88.54% and the EDP by up to 95.31% when compared to earlier domino. In terms of unity noise gain, the LVNIDL technique outperforms the earlier domino by 1.09 to 1.47 times.

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“…The amount of power required by a circuit when all of its inputs are set to zero is known as stand-by power [21,[24][25][26][27][28][29].…”

Section: Standby Powermentioning

confidence: 99%

The assessment of Noise Immunity in Domino Employing Silicon Nano Materials

Garg,

Gupta,

Pandey

et al. 2023

Preprint

View full text Add to dashboard Cite

show abstract

“…In this paper, the unity-noise gain (UNG) is used in comparing the noise immunity of the conventional and proposed schemes. It is defined as the amplitude of the input noise that causes a noise pulse with the same amplitude at the output node [67]. The noise level can be varied by changing the amplitude or the width of the noise pulse.…”

Section: The Noise Immunitymentioning

confidence: 99%

A Charge-Accumulation Based High-Performance CMOS Circuit

Sharroush

2022

Port-Said Engineering Research Journal

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There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from degraded performance. In this paper, a circuit that depends on charge accumulation is proposed as an alternative to conventional CMOS design. The proposed scheme is investigated quantitatively and verified by simulation using predictive technology model (PTM) of the 45 nm CMOS technology with a power-supply voltage, VDD, equal to 1 V. Although the proposed scheme suffers from more sensitivity to process variations compared to static CMOS, the comparative analysis and simulation results confirm the superiority of the proposed scheme from the points of view of speed, area, power consumption, and unity-noise gain. It is verified that the proposed scheme has a smaller area, power consumption, and delay compared to the conventional CMOS design when the number of inputs, n, exceeds four, two, and three, respectively. The impacts of process variations, component mismatches, and technology scaling are also investigated. The speed advantage gained from the proposed scheme is expected to be more obvious when operating in the subthreshold region. A figure of merit including the unity-noise gain, area, power consumption, and time delay is defined and the proposed scheme showed superior performance compared to the conventional CMOS logic when n exceeds four. Finally, the proposed scheme was compared with various previous schemes.

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“…This reduces the dynamic power dissipation and hence the total power consumption [20][21][22][23]. The modification of a domino logic circuit aims at improving the robustness and speed performance of the circuit [24][25][26][27][28][29].…”

Section: Introductionmentioning

confidence: 99%

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Angeline

Bhaaskaran

2019

ETRI Journal

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Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high‐speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high‐speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan‐in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

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Low power dynamic circuit for power efficient bit lines

Cited by 21 publications

References 14 publications

The assessment of Noise Immunity in Domino Employing Silicon Nano Materials

The assessment of Noise Immunity in Domino Employing Silicon Nano Materials

A Charge-Accumulation Based High-Performance CMOS Circuit

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

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