High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Abstract

Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high‐speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high‐speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan‐in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

Design impacts of delay invariant high‐speed clock delayed dual keeper domino circuit

“…In conventional domino logic circuits, variation in keeper current aggravates the current (delay) variability of the dynamic node due to the positive feedback loop gain ( T ) associated with the keeper circuit. Hence, the delay variability can be minimised by reducing the loop gain value of keeper feedback loop [10]. The gain of the keeper feedback loop of the conventional domino logic is given where A inv is the inverter gain, g mK is the transconductance of keeper device M K and Z X is the impedance at the dynamic node.…”

“…Hence, in addition to the low power consuming and high-speed characteristics, there exists immense necessity for designing variation tolerant domino keeper structures with reduced loop gain. This led to the design of various domino logic topologies with modification in the keeper circuit based on (i) delayed enabling of keeper circuit [6][7][8], (ii) abrupt keeper control mechanisms [9,10], (iii) reduced voltage swing of the keeper control signal [11], (iv) process variation tolerant keeper mechanisms [12][13][14][15], and (v) varying the threshold voltage of the keeper device [16][17][18]. Various other topologies have also been proposed in the literature, to augment the discharge path for increased operating speed and also to reduce the leakage current [19][20][21].…”

Clock Delayed Dual Keeper Domino Logic Design with Reduced Switching

“…If C 0 is one then it computes the compliment hence, if the input B is provided then it performs the subtraction operation. For multiplication, an array multiplier [6] is designed using half adder and full adder blocks as depicted in Fig.8. An array multiplier is preferred for its regular uniform architecture.…”

“…This leads to decreased speed performance. To alleviate this issue, various domino logic structures are proposed in the literature [4][5][6].…”