Background: Cesarean Section is the most commonly performed abdominal operation in women all over the world. Variable rates of cesarean section are reported between and within countries. Cesarean section at full cervical dilatation with an impacted fetal head can be technically difficult and is associated with increased trauma to the lower uterine segment and adjacent structures, as well as increased hemorrhage and infection.Methods: This is a comparative cross-sectional study comparing maternal and neonatal outcome between first stage and second stage cesarean section performed at Govt Medical College Thrissur.Results: In present study out of 90 cesarean sections 30 were performed in second stage and 60 in first stage.74 % were primigravida in second stage cs group. Arrest due to malposition was major indication for second stage (76% of cases). The most important complication among second stage cs group was PPH (76.7%) and majority of them needed blood transfusion. These complications were less in first stage cs group. Other Complications like increased duration of surgery (mean=53.3 min), post op fever (36% post op Wound infection (13.3%) was seen in second stage group. Fetal complications like low APGAR scores were seen in 16.7% of cases compared to first stage group and most of them needed resuscitation.Conclusions: Women undergoing cesarean section in second stage of labour had increased maternal and fetal morbidity. They required special care and hence Operation should ideally perform and supervised by an experienced obstetrician. Timely decision for cesarean section should be made especially when risk factors for failure to progress are present.

Clock Delayed Dual Keeper domino logic style with Static Switching mechanism (CDDK_SS) using delayed enabling of the keeper circuit and modified discharge path has been proposed in this paper. In CDDK domino circuit, the principle of delayed enabling of keeper circuit offers reduced contention between keeper circuit and Pull Down Network (PDN). The modified discharge path at the output node eradicates the switching at the output node for identical TRUE inputs during the pre-charge phase. This facilitates in obtaining static like output in contrast with conventional domino logic. The simulation results of Arithmetic and Logic Unit (ALU) subsystems demonstrate 17.7% reduction in dynamic power consumption while compared to conventional domino logic. Furthermore, 62% enhancement in speed performance has been achieved with good robustness. Design and simulation have been executed using Cadence® Virtuoso, with UMC 90nm technology node library.