Low power fast cryogenic CMOS circuit for digital readout of single electron transistor

Abstract

We present a cryogenic CMOS circuit with signif icant performance improvements compared to previously pro posed single-shot Single Electron Transistor readout circuit. The new readout architecture developed on commercial O.5J.tm SOl CMOS process is desinged to operate at 4.2K temperature and detect the SET signal current as low as 200pA. In addition to very low signal levels, the design process is complicated due to severe power consumption limitations at low temperature and J.tV level drain-source compliance requirement of the SET. The design addresses the low-temperature CMOS irregularities found in published literature and even under the design restrictions andSET specifications, our circuit shows successful digital detection of a SET event with only'" 520ns delay and consumes as low as 761' W power. In addition to speed improvement over previous design (detection time more than l0J.ts), this design is more robust and tolerant to biasing variations.

Waveguide integrated superconducting single-photon detectors implemented as near-perfect absorbers of coherent radiation

“…The silicon host material facilitates high-performance CPA-SNSPDs because of its high index contrast, while also offering the potential of integrating on-chip electronic circuits with the detectors to further boost the performance, and to handle the complexity of scaling up the read-out circuits. This latter point is especially interesting in light of studies that show the compatibility of CMOS 15 transistors with the cryogenic environment 63,64 . The projected superior speed performance of CPA based detectors combined with their built-in filtered QE, and advanced fiber to waveguide coupling methods 65 , will also make these detectors ideal for implementing fast quantum communication systems.…”

The electronic interface for quantum processors

“…For the read-out, an LNA fabricated in a 500-nm SOS CMOS process shows noise sufficiently low to measure the impedance of an SET in a measurement time of only ∼520 ns [115]. Another LNA, integrated in a bulk 160nm CMOS technology for the use in an RF-reflectometry read-out achieves a gain of 57 dB and bandwidth of 500 MHz at 4 K with an in-band noise figure of 0.1 dB (7 K noise temperature) [97].…”

Sub-Nanoampere One-Shot Single Electron Transistor Readout Electrometry Below 10 Kelvin

“…A brief review of associated design challenges due to unusual voltage-current behavior of MOS transistors at such low temperatures was also included [11]. The design was further improved in [12] to enable faster response and better signal integrity, while modifications necessary to cope with practical imperfections arising from a low temperature measurement setup were discussed in [13]. The performance degradation of analog CMOS circuits due to ultra low temperature operation may be prevented to some extent by including special circuitry, but cannot be avoided altogether.…”