Low-Power Field-Programmable VLSI Using Multiple Supply Voltages

Chong, Weisheng; Hariyama, Masanori; Kameyama, Michitaka

doi:10.1093/ietfec/e88-a.12.3298

Cited by 4 publications

(4 citation statements)

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“…That is the circuits precharge when Req=0, evaluate when Req=1. Since pulldown network is used, regardless the voltage of the supply voltage used in previous LBs and the current LB, no level-shifter is required for the LUT [7]. The behavior of the LUT is as follows.…”

Section: Circuit Implementationmentioning

confidence: 99%

“…Note that no software or complex off-line analyze is required. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a Look-Up- Table (LUT) without level shifters is employed [7]. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block.…”

Section: Introductionmentioning

confidence: 99%

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Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs

Ishihara¹,

Xia²,

Hariyama³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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Section: Circuit Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs

Ishihara¹,

Xia²,

Hariyama³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

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show abstract

“…That is the circuits pre-charges when Req = 0, evaluates when Req = 1. Since pull-down network is used, regardless the voltage of the supply voltage used in previous LBs and the current LB, no level-shifter is required for the LUT [3]. The operation of the LUT is as follows.…”

Section: B Self-adaptive Voltage Control and Its Implementationmentioning

confidence: 99%

“…Note that no software or complex off-line analyze is required. Moreover, to reduce to overhead of level shifter used at the power domain interface, a Look-Up- Table (LUT) without level shifters is employed [3]. Because of the small overhead of the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single 4-input-and-1-output logic block.…”

Section: Introductionmentioning

confidence: 99%

Architecture of a low-power FPGA based on self-adaptive voltage control

Ishihara

Xia

Hariyama

et al. 2009

2009 International SoC Design Conference (ISOCC)

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This paper presents a low-power FPGA with multiple supply voltages. In the proposed FPGA, the supply voltage of each logic block is self-adaptive to the workload, data path and temperature to minimize the power consumption without system performance degradation. In the self-adaptive voltage control scheme, features of the asynchronous architecture are exploited. The data arrival of the asynchronous architecture can be easily detected by detecting the change of the data's phase. By exploiting this feature, the critical path can be detected in real time. Logic blocks on the non-critical path are autonomously switched to a lower supply voltage to reduce the power consumption.

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