Low-power folded tree architecture and multi-bit flip-flop merging technique for WSN nodes

Abstract

Wireless communication exhibits the highest energy consumption in wireless sensor network (WSN) nodes. Due to their limited energy supply from batteries, the low power design have become inevitable part of today's wireless devices. Power has become a burning issue in VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. Reducing the power consumption not only enhance battery life but also avoid overheating problem. By employing a more appropriate Processing Element (PE), the power consumption is significantly reduced. In this paper the novel method for low power design is achieved by using Folded

Comprehensive Review of Optimal Utilization of Clock and Power Resources in Multi Bit Flip Flop Techniques

“…In SOC design the dynamic power consumption is dominated and 75% of power is contributed to the total power of the design (2) . Recent researches have introduced many approaches to reduce to switching rate in the clock network such as register placement optimization, buffer sizing [ (3)(4)(5) , register banks (6) , multi-bit flipflops (MBFFs), or applying multi-bit registers (7)(8)(9)(10)(11)(12)(13)(14)(15) . The concept of making a flip-flop of 2 bit from merging -bit flip-flops of two 1 bit is shown in Figure . 1.…”