Low-power gated clock tree optimization for three-dimensional integrated circuits

Chen, Yu-Chuan; Hsu, Chih‐Cheng

doi:10.1109/vlsi-dat.2015.7114530

Cited by 2 publications

(3 citation statements)

References 27 publications

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“…The power model of the clock network is based on [21]. The power consumption of gated clock network Pd clk t can be calculated by summing up the dynamic power from the clock source to each clock sink and total TSVs as shown in (3):…”

Section: Dynamic Power Consumption In Clock Networkmentioning

confidence: 99%

“…In [20], the authors proposed a heuristic approach for 3D clock tree synthesis aimed to minimise the number of TSVs and reduce the overhead for redundant trees. In [21], the authors proposed an algorithm for 3D‐gated clock tree optimisation. They considered both flip‐flop switching activities and the timing constraint of enabling signal paths at clock gating cells while constructing topological gated clock trees.…”

Section: Literature Surveymentioning

confidence: 99%

“…The power model of the clock network is based on [21]. The power consumption of gated clock network

P d_{normalcl k_{t}}

can be calculated by summing up the dynamic power from the clock source to each clock sink and total TSVs as shown in (3):

P d_{normalcl k_{t}} = 1 / 2 falsefalse{C_{lt} V^{2} f + N_{TSV} * normalCa p_{TSV} * V^{2} f falsefalse}

where

C_{l t}

is the 3D net load capacitance that encompasses both gates and interconnect and V is the power supply voltage, and f is the clock frequency.…”

Section: Preliminariesmentioning

confidence: 99%

See 2 more Smart Citations

An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC

Mondal

Chatterjee²,

Samanta

2018

IET Computers & Digital Techniques

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Effective clock tree design is an important factor for determining chip performance. In this study, the authors present a 3D clock tree design algorithm to enhance the speed and performance of a VLSI chip. The authors propose an algorithm to determine the performance of the clock network by optimising both the clock skew and the dynamic power consumption of the 3D IC clock tree. The authors propose an algorithm for clock tree design based on the Elmore Delay method and routes all the sinks efficiently considering the obstacles with the use of an optimum number of through-silicon-vias (TSVs). The proposed method starts with a segregation technique to divide the sinks into smaller zones. Subsequently, an obstacle avoiding abstract clock tree is constructed with a minimum number of TSVs and buffers. The skew and dynamic power of the tree is calculated. Consequently, the proposed method is compared with recent existing works. The experimental results so obtained are quite encouraging. Nomenclature SinkNode set of sinks die no number of die or stack s n any sink ∈ SinkNode x i , y i coordinates of sink s i Sink NEB , Sink NWB , Sink SEB , Sink SWB set of sinks at direction North East, North West, South East and South West Block, respectively (x lc , y lc) location of centre with x,y position WL wire length Res resistance Cap capacitance

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Section: Dynamic Power Consumption In Clock Networkmentioning

confidence: 99%

Section: Literature Surveymentioning

confidence: 99%

“…The power model of the clock network is based on [21]. The power consumption of gated clock network