Low power H.264 deblocking filter hardware implementations

Parlak, Mustafa; Hamzaoğlu, İlker

doi:10.1109/tce.2008.4560164

Cited by 37 publications

(6 citation statements)

References 9 publications

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“…Power consumption analysis of the proposed architecture and the architecture presented in [1] are carried out using Xilinx XPower tool by using the switching activity of the hardware architectures obtained using Mentor Graphics ModelSim simulator as described in [13]. The power consumption analysis for several search positions in a sample video frame is given in Table III for C-1BT.…”

Section: Implementation Resultsmentioning

confidence: 99%

Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms

Çelebi

Urhan

Hamzaoğlu

et al. 2009

IEEE Signal Process. Lett.

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In this paper, we present efficient hardware implementation of multiplication free one-bit transform (MF1BT) based and constraint one-bit transform (C-1BT) based motion estimation (ME) algorithms, in order to provide low bit-depth representation based full search block ME hardware for real-time video encoding. We used a source pixel based linear array (SPBLA) hardware architecture for low bit depth ME for the first time in the literature. The proposed SPBLA based implementation results in a genuine data flow scheme which significantly reduces the number of data reads from the current block memory, which in turn reduces the power consumption by at least 50% compared to conventional 1BT based ME hardware architecture presented in the literature. Because of the binary nature of low bit-depth ME algorithms, their hardware architectures are more efficient than existing 8 bits/pixel representation based ME architectures.Index Terms-Low bit-depth motion estimation, motion estimation hardware, source pixel based linear arrays.

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Section: Implementation Resultsmentioning

confidence: 99%

Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms

Çelebi

Urhan

Hamzaoğlu

et al. 2009

IEEE Signal Process. Lett.

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“…The video compression efficiency achieved in this standard is not the result of any single feature but rather a combination of a number of encoding tools and algorithms. Among these tools is the adaptive DBF algorithm [5]. The DBF is used to decrease blocking artifacts caused by other modules in H.264/AVC CODECs as shown in Figure 1.…”

Section: Deblocking Filter Used In H264 Codecsmentioning

confidence: 99%

“…Third, in order to decide whether the DBF will be applied to an edge, the related pixels in the current and neighboring blocks must be read from memory and processed. Because of these complexities, the DBF algorithm can easily account for one-third of the computational complexity of an H.264 video codec [5]. In some applications involving this filter, it might be necessary to use one of the two implementations of the module, in order to tune the performance of the system depending on the demands of the application.…”

Section: Introductionmentioning

confidence: 99%

Performance comparison of two hardware implementations of the deblocking filter used in H.264 by changing the utilized data width

Messaoudi

Bourennane

Toumi

et al. 2011

International Workshop on Systems, Signal Processing and Their Applications, WOSSPA

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The deblocking filter is more complex than other modules in the H.264 because it is highly adaptive, applied to each boundary of all 4x4 blocks and updated three pixels in each direction. After careful study and analysis of this filter, we have concluded that its complexity lies in the data dependency and in the control module of elementary filters that compose it, but not in the type of these filters. In this paper, we propose two hardware implementations for the deblocking filter using the same strategy for memory management. The implementations differ on the utilized data width. The first one utilizes 32-bit while the second one utilizes 128-bit. The use of 128-bit data width is in order to ensure a high degree of parallelism and to avoid the use of transpose circuits and the intermediate buffers between the elementary modules in the filter. Simulation and synthesis results are then compared. The number of consumed LUTs remains almost the same compared with previous implementations and the number of clock cycles required to process a macroblock is reduced about 40% less than the best of the competing proposals.

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“…2 T unit transposes pixels from rows to columns, and T 21 unit acts as the reverse function. A counter-based controller supplies necessary control signals to harmonise the whole operation of DBF.…”

Section: Dbf Architecture and Filtering Proceduresmentioning

confidence: 99%

Fast deblocking filter with highly parallel and pipelined architecture for H.264/AVC decoder

Meng

Zhang

2011

The Imaging Science Journal

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The deblocking filter (DBF) is a system bottleneck of the whole decoder in terms of processing cycles. Based on the study and analysis of the basic filtering order and previously presented filtering orders, we put forward a competitive filtering scheme to reduce the filtering cycles and improve the system throughput. Then, a highly parallel and pipelined deblocking filter architecture is proposed accordingly. Comparison of various DBF solutions shows that the system performance of our proposal significantly outperforms the previous designs from 3.7 to 8.3 times. Moreover, our architecture can easily support real-time deblocking of 60 fps HDTV video, and it can be suitably integrated into the H.264/AVC decoder.

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Low power H.264 deblocking filter hardware implementations

Cited by 37 publications

References 9 publications

Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms

Efficient Hardware Implementations of Low Bit Depth Motion Estimation Algorithms

Performance comparison of two hardware implementations of the deblocking filter used in H.264 by changing the utilized data width

Fast deblocking filter with highly parallel and pipelined architecture for H.264/AVC decoder

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