Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain

Purushothaman, Vijaya Kumar; Klumperink, Eric A.M.; Plompen, Roel; Nauta, Bram

doi:10.1109/jssc.2021.3091942

Cited by 31 publications

(6 citation statements)

References 31 publications

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“…This is a very promising result, even though the chip does not include neither VCO nor BB stage and it is expected that, when implementing the entire RX chain, to preserve low noise and high linearity, a significant power dissipation will be required in the BB stage. More recently the same idea was reported in [71], which includes the BB stage, and achieves 20−24 dBm OOB IIP3 while burning only 1.7−2.5 mW in the 1.8−2.8 GHz frequency range. Another example of capacitive stacking MFRX is reported in [53].…”

Section: Low Power Rx Building Blocks Design a Lnamentioning

confidence: 73%

Design Considerations for a Sub-mW Receiver Front-End for Internet-of-Things

Kargaran

Manstretta

Castello

2021

IEEE Open J. Solid-State Circuits Soc.

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Internet-of-Things (IoT) and Wireless sensor networks (WSNs) require very low power transceivers. This paper presents techniques for minimizing power consumption of receiver (RX) frontends for short range wireless links. Two key approaches, i.e., current reuse and supply voltage reduction are compared. Different RX architectures such as direct-conversion, low-IF, sliding IF as well as phasetracking RX, are compared, emphasizing their potential and limitations when targeting sub-mW RX power dissipation. Low-power design techniques for LNA, frequency generation blocks and baseband amplifiers are presented. As a case study, an efficient low-IF RX front-end for IoT is described in detail. In 28 nm CMOS, such a receiver occupies an active area of 0.1 mm 2 and consumes only 350 μW from a 0.9 V supply while showing a minimum in band NF of 6.2 dB. The achieved performance is very competitive with state-of-the-art ultra-low-power receivers, while consuming the lowest power.INDEX TERMS Ultra low-power (ULP), current reuse, gm-boosting, complex filter, IoT, ultra-low-voltage (ULV).

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Section: Low Power Rx Building Blocks Design a Lnamentioning

confidence: 73%

Design Considerations for a Sub-mW Receiver Front-End for Internet-of-Things

Kargaran

Manstretta

Castello

2021

IEEE Open J. Solid-State Circuits Soc.

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“…Conventional receivers (RXs) employ numerous off-chip surface-acoustic-wave (SAW) filters to suppress the out-of-band (OOB) blockers. To eliminate SAW filters, the switched-capacitor (SC) N-path techniques are commonly exploited in wideband RXs [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12]. due to the property of the local oscillator (LO)-defined frequency, sharp frequency selectivity and high linearity.…”

Section: Introductionmentioning

confidence: 99%

“…Alternatively, fully-passive RF front-ends are emerging as a promising approach to enhance linearity. In [10] and [11], an RF transformer and a BB capacitive-stacking network are utilized to produce a passive voltage gain of 13 dB, but with a ∼20 MHz passband centerfrequency shifting. In [12], a passive low-noise amplifier (LNA) is built by creating an N-path switched-capacitortransformer network, achieving 9.8 dB passive voltage gain, 3.4 to 4.8 dB NF and a high OB-IIP 3 of 23.5 dBm.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique

Mao,

Qi,

Mak

2024

IEEE Open J. Circuits Syst.

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This paper reports a wideband blocker-tolerant receiver (RX) that covers a 0.5-to-2 GHz radio frequency (RF) range. By combining the gain-boosted (GB) mixer-first low-noise amplifier (LNA) network with a bottom-plate switched-capacitor (SC) N-path filter, the proposed RX provides a high RF gain and high out-of-band (OOB) blocker suppression to improve both the noise figure (NF) and OOB linearity. Particularly, our RX features enhanced filtering at the input side that can effectively prevent the OOB blockers from entering into the RX. By deriving its linear time-invariant (LTI) model, the input impedance matching, gain response and noise performance are analyzed. Besides that, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Designed in 65-nm CMOS, the simulated results present that under an 80-MHz offset frequency, the RX scores a 29 dBm OOB-IIP 3 and a −2.3 dBm B −1 dB. The NF ranges between 3.2 to 6 dB, and the active area is 0.66 mm 2 . At 2 GHz, the power consumption is 25 mW, of which only 4.7 mW is due to the LO dynamic power.INDEX TERMS Bottom-plate, blocker-tolerant, gain-boosted (GB), linearity, low-noise amplifier (LNA), LO generator, N-path filter, OOB-IIP 3 , noise figure (NF), switched-capacitor (SC).

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“…It reports good 1-dB compression out-of-band linearity, but 51 a poor in-band 1-dB compression of −56 dBm is achieved at a maximum gain setting of 61 dB. Another approach [10] However, the front-end suffers from VCO injection locking 87 and a high NF of 9 dB. In addition, the common-source 88 LNTA used limits the RF bandwidth, which is not suitable to cover wide RF bandwidth with a single receiver module.…”

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confidence: 99%

A Wideband Low-Power RF-to-BB Current-Reuse Receiver Using an Active Inductor and 1 /f Noise-Cancellation for L-Band Applications

2022

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A low-power and wideband RF-to-baseband (BB) current-reuse receiver (CRR) front-end utilizing both a 1/f noise cancellation (NC) technique and an active inductor (AI) is proposed tuned to operate from 1 GHz to 1.7 GHz for L-Band applications, including those that require high modulation bandwidths. The CRR front-end employs a single supply and shares the bias current of the low noise transconductance amplifier (LNTA) with the BB circuits to reduce the power consumption. To minimize the losses of the radio frequency (RF) signal right before down-conversion, a high impedance AI circuit isolates the mixer input from the CRR output node. The 1/f NC circuit suppresses the low frequency noise of the LNTA that leaks to the output. A common-gate LNTA with g m -boosting, along with a single-to-differential LC-balun are used to enhance the input matching, conversion gain and noise figure (NF). The proposed receiver is fabricated in a TSMC 130 nm CMOS process and occupies an active area of 0.54mm 2 . The input matching (S 11 ) is below −10 dB from 1 GHz to 1.7 GHz. At a local-oscilator (LO) frequency of 1.3 GHz, intermediate-frequency (IF) of 10 MHz and default current settings, the CRR achieves a conversion gain of 41.5 dB, a doublesideband (DSB) NF of 6.5 dB, and an IIP3 of −28.2 dBm while consuming 1.66 mA from a 1.2 V supply. 14 15 employed a current-reuse baseband amplifier in a mixer-first 54 receiver architecture. It achieves very good performance con-55 suming a low-power of 0.38 mW. However, the receiver 56 architecture is not suitable for wideband modulations as it 57 reports a very low baseband bandwidth of 2 MHz that is 58 not suitable for wider modulation bandwidth applications. 59 In [11], a quadrature low noise amplifier (LNA) and active-60 type poly-phase filter (PPF) were used to reduce power con-61 sumption. However, the receiver has a narrow RF bandwidth 62 due to the common-source LNA topology, and high NF 63 because of the quadrature technique used in the LNA. In [12], 64 alternatively, an inverter-based LNA with an LC-balun and 65 passive PPF are used to generate the quadrature signal before 66 the down conversion. This reduces the LO dynamic power 67 for Bluetooth low-energy (BLE), but using an LC-balun and 68 passive PPF is not suitable for wideband applications. In addi-69 tion, a phase-locked loop (PLL) free receiver architecture is 70 proposed in [13] at the cost of a high NF. 71 Recently, current sharing of RF and BB blocks using a sin-72 gle supply voltage has been actively studied. Conventionally, 73 receiver front-ends cascade circuits to receive and amplify a 74 weak RF signal with a LNTA, down-convert it to BB through 75 a mixer and finally convert the current signal to a voltage 76 signal using a transimpedance amplifier (TIA), as shown 77 in Fig. 1. On the other hand, by scaling down the CMOS 78 technology node where the voltage threshold is reduced and 79 transition frequency (f T ) is increased, stacked architectures 80 that reduce power consumption by sharing the current of the 81 RF ci...

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Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain

Cited by 31 publications

References 31 publications

Design Considerations for a Sub-mW Receiver Front-End for Internet-of-Things

Design Considerations for a Sub-mW Receiver Front-End for Internet-of-Things

Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique

A Wideband Low-Power RF-to-BB Current-Reuse Receiver Using an Active Inductor and 1 /f Noise-Cancellation for L-Band Applications

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