Low power high-speed 10 Gb/s 4∶1 multiplexer for sliding-IF digital centric transmitter in 65nm CMOS

Bousseaud, Pierre; Negra, Renato

doi:10.1109/gemic.2016.7461628

Cited by 2 publications

(5 citation statements)

References 8 publications

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“…It can be seen that the proposed circuit performs better. In terms of power dissipation, the proposed multiplexer circuit has a power dissipation of 7.067 nW, whereas Bousseaud and Negra 7 had a value of 5 mW. The approach used by Bousseaud and Negra 7 used a transmission gate, while pass transistor logic is used in the proposed circuit.…”

Section: Resultsmentioning

confidence: 99%

“…In terms of power dissipation, the proposed multiplexer circuit has a power dissipation of 7.067 nW, whereas Bousseaud and Negra 7 had a value of 5 mW. The approach used by Bousseaud and Negra 7 used a transmission gate, while pass transistor logic is used in the proposed circuit. Pass Transistor Logic (PTL) does provide an advantage in the design of circuits with the elimination of redundant transistors.…”

Section: Resultsmentioning

confidence: 99%

“…2 The analogue MUX/DEMUX was designed using ternary inverters to control the circuits, and CMOS transmission gates were used. [6][7][8] The design improved and proved to be excellent for ternary inverters. With the idea of switching activities suggested by Anitha and Javachitra, 9 adiabatic logic reduces the power by offering back the stored energy to the supply and this was used for the 16:1 multiplexer and 1:16 demultiplexer.…”

Section: Literature Reviewmentioning

confidence: 99%

“…A demultiplexer has been designed with 36 transistors using 90 nm CMOS technology. 7 Auto-generation technique and semi-custom layout design were integrated. There was an improvement in power consumption and area due to the semi-customized demultiplexer layout.…”

Section: Introductionmentioning

confidence: 99%

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Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

2022

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Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Literature Reviewmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

2022

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show abstract

“…2 The analogue MUX/DEMUX was designed using ternary inverters to control the circuits, and CMOS transmission gates were used. [6][7][8] The design improved and proved excellent for ternary inverters. With the idea of switching activities suggested by Anitha and Javachitra, 9 adiabatic logic reduces the power by offering back the stored energy to the supply, and this was used for the 16:1 multiplexer and 1:16 demultiplexer.…”

Section: Literature Reviewmentioning

confidence: 99%

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

2022

View full text Add to dashboard Cite

show abstract

Low power high-speed 10 Gb/s 4∶1 multiplexer for sliding-IF digital centric transmitter in 65nm CMOS

Cited by 2 publications

References 8 publications

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders

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