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In this paper, a digital up-sampling technique is presented for digital communication transmitters. This method allows to up-sample the I/Q baseband modulated signals to an intermediate frequency based on a 4:1 multiplexing technique, before being again up-converted at the carrier frequency. The frequency conversion is made in two steps and permits to avoid the nonlinear behavior of direct up-converting architectures. Also, the mutual coupling between the output power amplifier (PA) and the phase-locked loop (PLL) can be reduced by choosing the local oscillator frequency (LO) far enough from the carrier output frequency. A fully integrated CMOS transmitter with an on chip PA is thus becoming feasible. A PLL at the frequency of 4.8 GHz has been designed in a 65 nm CMOS process along with a digital 4:1 multiplexer in order to target the band-VII Long Term Evolution (LTE) applications in the 2.55 GHz frequency.

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