Low power/high speed optimization approaches of MISTY algorithm

Rjoub, Abdoul; Ghabashneh, Ehab M.

doi:10.1109/icedsa.2016.7818520

Cited by 4 publications

(4 citation statements)

References 7 publications

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“…A detailed study has been carried out on the existing hardware designs of MISTY1, KASUMI, AES, SHA-1, CAMELLIA and SAFER [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. The review covered the comparison of performance parameters i.e.…”

Section: Introductionmentioning

confidence: 99%

“…In comparison to high throughput encryption cores, compact designs make use of the logic optimization techniques for transformation functions and s-boxes using combinational logic [5][6][7][8][9][10], [12][13][14][15][16][17][18], [21], [22]. Besides, re-utilization methodologies have also been implemented exploiting the rolling-feature of the architecture.…”

Section: Introductionmentioning

confidence: 99%

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Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Yasir¹,

Wu²,

Chen³

et al. 2018

RADIOENGINEERING

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In this paper, state-of-the-art hardware implementations of MISTY1 block cipher are presented for areaconstrained wireless applications. The proposed MISTY1 architectures are characterized of highly optimized transformation functions i.e. FL and {FO-XOR-EKG}. The FL function re-utilizes logic AND-OR-XOR combinations whereas {FO-XOR-EKG} function explores 2 × compact design schemes for s-boxes implementation. A Combined Substitution Unit (CSU) and threshold area implementation are proposed for s-boxes based on Boolean reductions and Common Sub-expression Eliminations (CSEs). Besides, {FO-XOR-EKG} function is designed for manifold operations of FO / FI functions, 32-bit XOR operation and extended key generation thereby reducing the area. Hardware implementations on ASIC 180nm, 1.8V standard library cell realized compact and threshold MISTY1 designs constituting 1853 and 1546 NAND gates with throughput values of 41.6 Mbps and 4.72 Mbps respectively. A comprehensive comparison with existing cryptographic hardware designs establishes that the proposed MISTY1 architectures are the most area-efficient implementations till date.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Yasir¹,

Wu²,

Chen³

et al. 2018

RADIOENGINEERING

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show abstract

“…The design and optimization of cryptographic algorithms have been studied in detail keeping in view the application requirements for low area, high speed or achieving a trade-off between area and speed [2,3,4,5,6,7,8,9,10,11]. For low area design, the commonly adopted methods include re-utilization of logic blocks and s-boxes optimization [2,3,4,5,6,7].…”

Section: Introductionmentioning

confidence: 99%

“…For low area design, the commonly adopted methods include re-utilization of logic blocks and s-boxes optimization [2,3,4,5,6,7]. The area-efficient implementation techniques have widely been adapted to a feistel-like MISTY1 structure using a single FI/FO function for embedded applications [2,3,4].…”

Section: Introductionmentioning

confidence: 99%

FPGA based highly efficient MISTY1 architecture

Yasir

Chen

et al. 2017

IEICE Electron. Express

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This letter proposes highly efficient MISTY1 8-rounds pipelined architecture for wireless networks. A novel methodology is adopted for implementation of MISTY1 substitution functions by optimizing S9 and S7 LUTs (Look-Up Tables) to minimize the silicon area. Besides, a key module FI function is compliant to double edge-trigger the optimized S9 LUTs. This leads to substantial reduction in the pipeline requirements for the proposed hardware architecture. For path delay reduction, logic modifications are made in FI and FO functions realizing efficient and high-speed MISTY1 implementation. FPGA implementation on Xilinx FPGA, Virtex 7 xc7vx690t yielded a throughput value of 16.3 Gbps covering area of 1265 CLB slices.

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Compact and High Speed Architectures of KASUMI Block Cipher

Yasir

Ali

et al. 2018

Wireless Pers Commun

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Low power/high speed optimization approaches of MISTY algorithm

Cited by 4 publications

References 7 publications

Area-Efficient Hardware Architectures of MISTY1 Block Cipher

Area-Efficient Hardware Architectures of MISTY1 Block Cipher

FPGA based highly efficient MISTY1 architecture

Compact and High Speed Architectures of KASUMI Block Cipher

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