Low Power, High-Speed Radiation Hardened Computer &amp;amp;amp; Flight Experiment

Albanese²,

Alderighi

et al. 2015

IEEE Trans. Nucl. Sci.

Commercial-off-the-shelf devices are often advocated as the only solution to the increasing performance requirements in space applications. This paper presents the solutions developed in the frame of the European Space Agency's HiRel program, concluded in December 2014, in which a number of techniques proposed in the past 10 years have been used to design a highly reliable system, which has been selected for forthcoming space missions. The paper presents the system architecture, describes performed evaluations and discusses the results.

Section: ) Hybrid Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

COTS-Based High-Performance Computing for Space Applications

Albanese²,

Alderighi

et al. 2015

IEEE Trans. Nucl. Sci.

“…VDS and TMR can be combined in Temporal Triple Module Redundancy (TTMR) [6]. In TTMR, two executions are performed and the outputs are compared for agreement, as described for VDS.…”

Section: Previous Workmentioning

confidence: 99%

On the Consolidation of Mixed Criticalities Applications on Multicore Architectures

Violante

2017

J Electron Test

In this paper we propose a hybrid solution to ensure results correctness when deploying several applications with different safety requirements on a single multi-core-based system. The proposed solution is based on lightweight hardware redundancy, implemented using smart watchdogs and voter logic, combined with software redundancy. Two techniques of software redundancy are used: the first one is software temporal triple modular redundancy, used for those tasks with low criticality and no real-time requirement. The second software redundancy technique is triple module redundancy for tasks with high criticality and real-time requirements, assisted by a hardware voter. A hypervisor is used to separate each task in the system in an independent resource partition, thus ensuring that no functional interference is occurring. The proposed solution has been evaluated through hardware and software fault injection on two hardware platforms, featuring a dual-core processor and a quad-core processor respectively. Results show a high fault tolerance achieved using the proposed architecture.

“…The system uses two main approaches to fault tolerance, mainly software implemented. The first approach is a merge of Dual Duplex Tolerant to Transients (DT2) [14] and Temporal Triple Modular Redundancy (TTMR) [15], as depicted in Fig. 1.…”

Section: A Software Implemented Fault Tolerancementioning

confidence: 99%

System-level architecture for mixed criticality applications on MPSoC: A space application

2017 IEEE International Workshop on Metrology for AeroSpace (MetroAeroSpace)

Violante

2017

This paper discusses SEE effects in an architecture based on commercial-off-the-shelf multicore processors for consolidating mixed criticalities applications in single board computers for space applications. This paper builds on previously proposed system-level architectures for mixed-criticality applications, describing them both for convenience together with the previous validation results. The paper proposes a case study on a real space application. Based on reliability and availability requirements of a European Space Agency mission, the paper shows how the proposed solutions can meet availability requirements in two different radiation environments.