Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks

Kim, Min Soo; Barrio, Alberto A. Del; Hermida, R.; Bagherzadeh, Nader

doi:10.1109/aspdac.2018.8297391

Cited by 27 publications

(15 citation statements)

References 40 publications

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“…One of the solutions is approximate FP arithmetic [11]- [15], which is based on the fact that there is no need to waste energy to reach 100% accuracy as it is not always required [16]. Many applications in multimedia and ML fields have adopted this concept [16], [17].…”

Section: Introductionmentioning

confidence: 99%

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An Approximate and Iterative Posit Multiplier Architecture for FPGAs

Norris

Kim

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Recently, many applications have demanded cheaper and faster arithmetic while providing a wider dynamic range than the popular IEEE 754 floating-point (FP) arithmetic. As a result, a new number format called posit was proposed. As in a variety of number systems, multiplication in posit arithmetic is one of the most frequently used but expensive operations. To reduce the number of hardware resources in a posit multiplier, this paper applies an iterative approach to posit multiplication. To exploit the features of the posit format, the number of truncated bits in the fraction component is dynamically changed depending on the number of regime bits. In addition, architectures for fast parser and packer are proposed. Thanks to the posit format, the proposed design supports about 60 decades wider dynamic range than a single-precision FP multiplier design. Using the iterative approach, the proposed design also reduces the number of lookup tables used in a previous exact posit multiplier design by 44% while achieving a 51% higher maximum frequency, and the appropriate balance between latency and accuracy can be finely determined at runtime. To the best of the authors' knowledge, this paper is the first work that proposes a hardware architecture of an approximate and iterative posit multiplier.

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Section: Introductionmentioning

confidence: 99%

“…In many applications, multiplication is one of the most frequently used but expensive operations. Therefore, there have been a lot of studies on custom hardware accelerators of approximate multipliers [11]- [15], [17]- [19]. For FP multiplication, a popular approach is to approximate mantissa multiplication [11]- [13].…”

Section: Introductionmentioning

confidence: 99%

An Approximate and Iterative Posit Multiplier Architecture for FPGAs

Norris

Kim

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…The approximate logarithmic multiplier replaced the significand multiplication by adding input fractions [12]- [17]. It was proved that the approximate logarithmic multiplier could achieve reasonable performances in CNN inference [14]- [17] with pre-trained models. Several existing works focused on the unbiased design of the approximate dynamic ranged multiplier and its digital signal processing (DSP) applications [11], [18].…”

Section: Introductionmentioning

confidence: 99%

A Cost-Efficient Approximate Dynamic Ranged Multiplication and Approximation-Aware Training on Convolutional Neural Networks

Kim¹,

Barrio

2021

IEEE Access

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This paper proposes a low-cost approximate dynamic ranged multiplier and describes its use during the training process on convolutional neural networks (CNNs). It has been noted that the approximate multiplier can be used in the convolution of CNN's forward path. However, in CNN inference on a post-training quantization with a pre-trained model, erroneous convolution output from highly approximate multipliers significantly degrades performance. On the other hand, with the CNN model based on an approximate multiplier, the approximation-aware training process can optimize its learnable parameters, producing better classification results considering the approximate hardware. We analyze the error distribution of the approximate dynamic ranged multiplication and characterize it in order to find the most suitable approximate multiplier design. Considering the effects of normalizing the biased convolution outputs, a low standard deviation of relative errors with respect to the multiplication outputs leads to negligible accuracy drop. Based on these facts, the hardware costs of the proposed multiplier can be further reduced by adopting the partial products' inaccurate compression, truncated input fraction, and reduced-width multiplication output. When the proposed approximate multiplier is applied to the residual convolutional neural networks for the CIFAR-100 and Tiny-ImageNet datasets, the accuracy drops of the approximation-aware training results are negligible compared to those using 32-bit floating-point CNNs.INDEX TERMS Approximate computing, approximate multiplier, approximation-aware training, convolutional neural network, probabilistic multiplier.

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“…Currently the efforts have moved from improving the accuracy to lighten the neural networks [13] and accelerate inference times [9] , [14] , which leads to further degrading the performance of the system when many faces need to be analyzed. Moreover, the previously mentioned decrease in performance is associated with an increase in the power consumption, which is very relevant when talking about monitoring applications.…”

Section: Introductionmentioning

confidence: 99%

CNN Inference acceleration using low-power devices for human monitoring and security scenarios

Mas

Panadero²,

Botella

et al. 2020

Computers & Electrical Engineering

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Security is currently one of the top concerns in our society. From governmental installations to private companies and medical institutions, they all have to address directly with security issues as: access to restricted information quarantine control, or criminal tracking. As an example, identifying patients is critical in hospitals or geriatrics in order to isolate infected people, which has proven to be a non- trivial issue with the COVID-19 pandemic that is currently affecting all countries, or to locate fled patients. Face recognition is then a non-intrusive alternative for performing these tasks. Although FaceNet from Google has proved to be almost perfect, in a multi-face scenario its performance decays rapidly. In order to mitigate this loss of performance, in this paper a cluster based on the Neural Computer Stick version 2 and OpenVINO by Intel is proposed. A detailed power and runtime study is shown for two programming models, namely: multithreading and multiprocessing. Furthermore, 3 different hosts have been considered. In the most efficient configuration, an average of 6 frames per second has been achieved using the Raspberry Pi 4 as host and with a power consumption of just 11.2W, increasing by a factor of 3.3X the energy efficiency with respect to a PC-based solution in a multi-face scenario.

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Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks

Cited by 27 publications

References 40 publications

An Approximate and Iterative Posit Multiplier Architecture for FPGAs

An Approximate and Iterative Posit Multiplier Architecture for FPGAs

A Cost-Efficient Approximate Dynamic Ranged Multiplication and Approximation-Aware Training on Convolutional Neural Networks

CNN Inference acceleration using low-power devices for human monitoring and security scenarios

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