Low Power Karnaugh Map Approximate Adder for Error Compensation in Loop Accumulations

Yang, Chun-Mei; Jiao, Hailong

doi:10.1109/icicdt.2019.8790952

Cited by 6 publications

(2 citation statements)

References 13 publications

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“…But for dealing with a large number of variables, there is no definition. To minimize different circuit outputs, the author [22] suggested an Expanded K-MAP that uses a single Karnaugh map. And essentially, in their algorithm, the multiple Karnaugh-maps accumulated in a single Karnaugh-map.…”

Section: Related Workmentioning

confidence: 99%

Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

Islam

Hussain

Sultana

et al. 2021

GUB JOURNAL OF SCIENCE AND ENGINEERING

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In computerized integrated circuits, the fundamental principle intends to avoid the multifaceted nature of the circuitry by making it as brief as attainable and minimize the expenditure. Techniques like Quine- McCluskey (QM) and Karnaugh Map (K-Map) are often used approaches of simplifying Boolean functions. This study presents a recreation framework of simplification of the Boolean capacities by the utilize of the K- Map definition for beginner-level learners. It uses the algebraic expression of the Boolean function to decrease the number of terms, generates a circuit, and does not use any redundant sets. In this way, it gets to be competent to deal with lots of parameters and minimize the computational cost. The result of the assessment is performed in this paper by contrasting it with the C- Minimizer algorithm. In computation time terms, the result appears that our comprehensive K mapping tool outflanks in current procedures, and the relative error accomplishes a lower rate of percentage (2%), which fulfills the satisfactory level. GUB JOURNAL OF SCIENCE AND ENGINEERING, Vol 7, Dec 2020 P 76-84

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Section: Related Workmentioning

confidence: 99%

Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

Islam

Hussain

Sultana

et al. 2021

GUB JOURNAL OF SCIENCE AND ENGINEERING

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show abstract

“…In proposed approximate adder, the power consumption is reduced by over to42.8 and24.9 when compared to completely-accurate adder and the preliminarily published approximate adders, independently, in an artificial 65-nm CMOS technology. By using the product of regularized mean error distance( NMED) and power consumption as the Figure-of-Merit( FoM), the proposed approximate adder improves the FoM up to37.7 x when compared to the preliminarily published approximate adders [6]. HonglanJiangetal.,( 2018) has proposed the Approximate circuits which has been considered for multitudinous operations that can tolerate some loss of delicacy with bettered performance and energy effectiveness.…”

Section: Introductionmentioning

confidence: 99%

Low Power Digital Image Compression Using Approximate Adders

T¹

2022

IJRASET

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Low power is one of the arising trend in field of VLSI which can be used in multimedia bias employing colorful signal processing algorithms and armature. In utmost multimedia operation mortal beings can gather useful information from incorrect afFull Adderir. Thus we don’t need to produce an exact correct numerical afFull Adderir. So we're using different adders to apply this algorithm in signal processing. We design infrastructures for videotape and image contraction algorithms using the proposed approximate computation units and estimate them to demonstrate the efficiency of our approach. We also decide simple fine models for error and power consumption of these approximate adders. The approximate adders are reduced with complexity which are used in designing this algorithm. The proposed adders can achieve significant through afFull Adderir and total power reduction over conventional adders. Simulation results indicate up to 69% power savings using the proposed approximate adders, when compared to being executions using accurate adders.

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Lower-part approximate multi-bit adders for low-power DSP

Gowdar¹,

Parameshwara²

2022

Int. j. inf. tecnol.

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Low Power Karnaugh Map Approximate Adder for Error Compensation in Loop Accumulations

Cited by 6 publications

References 13 publications

Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

Low Power Digital Image Compression Using Approximate Adders

Lower-part approximate multi-bit adders for low-power DSP

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