Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units

Dimitrakopoulos, Giorgos; Galanopoulos, Kostas; Mavrokefalidis, Christos; Nikolos, D.

doi:10.1109/tvlsi.2008.2000458

Cited by 39 publications

(30 citation statements)

References 24 publications

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“…(2) It computes the length of the first horizontal segment of consecutive zeros for each bit-vector (i.e., each HRT) using a leading-zero counter (LZC). Snake-on-Chip uses the LZC design proposed in (Dimitrakopoulos et al, 2008) as it requires low number of both logic gates and logic levels. It counts the number of consecutive zeros that appear in a t-bit input vector before the first more significant bit that is equal to one.…”

Section: Snake-on-chip Hardware Architecturementioning

confidence: 99%

SneakySnake: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs

Alser¹,

Shahroodi²,

Gómez-Luna³

et al. 2019

Preprint

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The ability to generate massive amounts of sequencing data continues to overwhelm the processing capacity of existing algorithms and compute infrastructures. Calculating the similarities between a pair of genomic sequences is one of the most fundamental computational steps in genomic analysis. This step -called sequence alignment-is formulated as an approximate string matching (ASM) problem, which is typically solved using computationally expensive dynamic programming algorithms. In this work, we introduce SneakySnake, a highly parallel and highly accurate pre-alignment filter that remarkably reduces the need for the computationally costly sequence alignment step. The key idea of SneakySnake is to provide fast and highly accurate filtering by reducing the ASM problem to the single net routing (SNR) problem in VLSI chip layout. In the SNR problem, we are interested in only finding the path that connects two terminals with the least routing cost on a special grid layout that contains obstacles. The SneakySnake algorithm quickly and optimally solves the SNR problem and uses the found optimal path to decide whether performing sequence alignment is necessary. We also build two new hardware accelerator designs, Snake-on-Chip and Snake-on-GPU, that adopts modern FPGA (field-programmable gate array) and GPU (graphics processing unit) architectures, respectively, to further boost the performance of our algorithm.SneakySnake significantly improves the accuracy of pre-alignment filtering by up to four orders of magnitude compared to the state-of-the-art pre-alignment filters, Shouji, GateKeeper, and SHD. SneakySnake accelerates the state-of-the-art CPU-based sequence aligners, Edlib and Parasail, by up to 37.6× and 43.9×, respectively, without requiring hardware acceleration. The addition of Snake-on-Chip and Snake-on-GPU as a pre-alignment filter reduces the execution time of four state-of-the-art sequence aligners, designed for different computing platforms, by up to 689× (101× on average).To our knowledge, SneakySnake is the fastest and most accurate pre-alignment filtering mechanism that greatly enables the speeding up of genome sequence alignment while preserving its accuracy. It is the only pre-alignment filtering mechanism that is universal, as it works on all modern high-performance computing architectures, i.e., CPUs, GPUs, and FPGAs, by having software as well as software/hardware co-designed versions. Unlike most existing works that aim to accelerate sequence alignment, SneakySnake does not sacrifice any of the aligner capabilities (i.e., scoring and backtracking), as it does not modify or replace the aligner. The three versions of SneakySnake are open source and freely available online at https://github.com/CMU-SAFARI/SneakySnake/.

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Section: Snake-on-chip Hardware Architecturementioning

confidence: 99%

SneakySnake: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs

Alser¹,

Shahroodi²,

Gómez-Luna³

et al. 2019

Preprint

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“…The shifted mantissa fA_sh and fB_sh are passed to a 25-bit flagged prefix adder FPPA_F and two leading zero detectors (LZD). The LZD is consist of a leading zero anticipator (LZA) [10] and a leading zero counter (LZC) [11]. The first LZD (LZA NEG þ LZC NEG) is used for the situation that fA is smaller than fB and the exponent difference is zero.…”

Section: Implementation Detailsmentioning

confidence: 99%

Delay-optimized floating point fused add-subtract unit

Wang

Zuo

2015

IEICE Electron. Express

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This paper presents a delay-optimized floating point fused addsubtract (FAS) unit. A FAS unit is very useful for FFT and DCT butterfly operations since it can perform addition and subtraction of two floating point numbers simultaneously. The latency of critical path is reduced by using injection-based rounding method and performing parallel exponent adjustment. The proposed FAS is modeled in Verilog-HDL and synthesized using TSMC 65 nm technology library. Synthesis results show that the proposed FAS requires roughly 60% area of two discrete adders. Comparison results show that our proposed FAS unit is 30% faster and 56% less area than the fastest FAS in previous work.

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“…The LZD produces the leading zero count which becomes the shift amount of the normalization. For the LZD, any type of tree logic can be used as discussed in the previous work [16], [17]. In this paper, for fast normalization, a LZD logic producing the MSBs of the shift amount first is selected so that the LZD logic and the normalization shifter are overlapped [4].…”

Section: Three-input Lza and Significand Comparisonmentioning

confidence: 99%

A Fused Floating-Point Three-Term Adder

Sohn

Swartzlander

2014

IEEE Trans. Circuits Syst. I

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This paper presents improved architectures for a fused floating-point three-term adder. The fused floating-point three-term adder performs two additions in a single unit to achieve better performance and better accuracy compared to a network of traditional floating-point two-term adders, which is referred to as a discrete design. In order to further improve the performance of the three-term adder, several optimization techniques are applied including a new exponent compare and significand alignment, dual-reduction, early normalization, three-input leading zero anticipation, compound addition/rounding and pipelining. The proposed design is implemented for both single and double precision and synthesized with a 45 nm CMOS standard-cell library. The improved fused floating-point three-term adder reduces the area and power consumption by about 20% and reduces the latency by about 35% compared to a discrete floating-point three-term adder. Based on the data flow analysis, the proposed three-term adder can be split into three pipeline stages. Since the latencies of three pipeline stages are fairly well balanced, the throughput is increased to 2.7 times that of the non-pipelined design.Index Terms-Floating-point arithmetic, fused floating-point operations, high speed computer arithmetic, three-term adder.

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Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units

Cited by 39 publications

References 24 publications

SneakySnake: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs

SneakySnake: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs

Delay-optimized floating point fused add-subtract unit

A Fused Floating-Point Three-Term Adder

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