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This paper presents improved architectures for a fused floating-point three-term adder. The fused floating-point three-term adder performs two additions in a single unit to achieve better performance and better accuracy compared to a network of traditional floating-point two-term adders, which is referred to as a discrete design. In order to further improve the performance of the three-term adder, several optimization techniques are applied including a new exponent compare and significand alignment, dual-reduction, early normalization, three-input leading zero anticipation, compound addition/rounding and pipelining. The proposed design is implemented for both single and double precision and synthesized with a 45 nm CMOS standard-cell library. The improved fused floating-point three-term adder reduces the area and power consumption by about 20% and reduces the latency by about 35% compared to a discrete floating-point three-term adder. Based on the data flow analysis, the proposed three-term adder can be split into three pipeline stages. Since the latencies of three pipeline stages are fairly well balanced, the throughput is increased to 2.7 times that of the non-pipelined design.Index Terms-Floating-point arithmetic, fused floating-point operations, high speed computer arithmetic, three-term adder.

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