Low power multi threshold 7T SRAM cell

Sachan, Divyesh; Peta, Harish; Malik, Kamaldeep Singh; Goswami, Manish

doi:10.1109/mwscas.2016.7870004

Cited by 11 publications

(2 citation statements)

References 9 publications

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“…The work proposed in [1], [4] is about discussing the design & implementation of 16X16 SRAM Array to store 256 bits. The proposed array [1] is built using Conventional 6T SRAM Cell.The work carried in [2] demonstrates the design of 16x16 SRAM based Array on Conventional 7T SRAM Cells.…”

Section: Related Workmentioning

confidence: 99%

“…In the present context of the work the comparative power analysis of 16x16 SRAM Array is carried with basic 7T, 7T-SVL, and 7T-ISVL. Single row of the proposed designed memory array has 16 cells further these 16 rows of 16 cells are used to form 16X16 SRAM Array [4].Individual SRAM cell in each row of 16X16 SRAM Array is arranged in the form of horizontal rows and vertical columns, accessed via row and Column decoder. In general SRAM Array has 2 N rows called as word lines and 2 M columns referred as bit lines [2].Generally Memory Array is built up with Basic cell, Row-column decoder, Pre-charge circuit and Sense amplifier.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

7T Based SRAM Topologies with Low Power and Higher SNM

S¹,

Kariyappa²

2019

IJITEE

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 Abstract: Now the era is of electronic gadgets like processors and portable devices, in which Memory plays a significant role through the usage of Static RAMs (SRAMs).Hence designing of Low power SRAM is immense for applications. But the design of SRAM is involved in higher power requirement. So there is still scope for adequate Low power Memory Array design. The Main Moto of this paper is involved in designing & Simulating Low Power 16x16 SRAM Arrays using 7T SRAM cells based on Conventional, Self Controllable Voltage (SVL) & Improved Self Controllable Voltage (I-SVL) methods. Also Comparative Power and SNM Analysis is carried between Conventional 7T, 7T-SVL and 7T-ISVL based Arrays. The Proposed Array using 7T Cell consumes 6.24mW which is 67.64% lesser than the Array design [2].Also I-SVL based 7T SNM is better than the SVL-7T and 7T based cell.The proposed work is carried using cadence virtuoso tool with standard library gpdk 180nm.Also Proposed Array based on I-SVL is efficient in terms of power. The proposed Cell SNM resulted in 68.57% higher in comparison with existing cell of 8T and 10T [3].

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%