In this article, we present an efficient way of implementing 90°phase shifter using Hilbert transformer with canonic signed digit (CSD) coefficients in FPGA. It is implemented using 27-tap symmetric finite impulse response (FIR) filter. Representing the filter coefficients by CSD eliminates the need for multipliers and the filter is implemented using shifters and adders/subtractors. The simulated results for the frequency response of the Hilbert transformer with infinite precision coefficients and CSD coefficients agree with each other. The proposed architecture requires less hardware as one adder is saved for the realization of every negative coefficient compared to convectional CSD FIR filter implementation. Also, it offers a high accuracy of phase shift.

This paper presents an architecture for generating UWB pulses with a high centre frequency accuracy. The architecture allows to generate frequencies twice that of the FPGA clock using synchronous delays and is implementable in all types of FPGA. With a FPGA clock of 150 MHz, we generate RF pulse of 300 MHz with a maximum fractional bandwidth of 30%. The architecture also allows pulse width increment in steps of the clock period.

No abstract