Efficient implementation of 90° phase shifter in FPGA

Duraiswamy, Punithavathi; Bauwelinck, Johan; Vandewege, Jan

doi:10.1186/1687-6180-2011-32

Cited by 12 publications

(9 citation statements)

References 8 publications

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“…To verify the functionality of proposed parallel adder in Digital Signal Processing application, an implementation in 27 tap finite impulse response (FIR) filter [15, 26] is done. The architecture of FIR filter is shown in Fig.…”

Section: Fpga Implementation In Digital Image Processingmentioning

confidence: 99%

Area‐efficient parallel adder with faithful approximation for image and signal processing applications

Palanisamy¹,

Natarajan²,

Sundaram³

2019

IET image process

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Design of low‐power and area‐efficient portable complementary metal–oxide–semiconductor processors for image and signal processing applications demand reduction in transistor switching and count. Adder is the fundamental block of all arithmetic operations performed in processing units. In this study, an error‐tolerant parallel adder with faithful approximation is proposed that can optimise area and accuracy. In the proposed parallel adder, for n bit input and m bit adder block, least n/2m blocks are designed with approximate logic using carry by‐pass addition algorithm and most n/2m blocks are designed with exact logic using carry select addition algorithm. Least significant approximate part of the adder is designed with either exact full adder (EFA) or fault‐tolerant full adder (FTFA) cells. This confines the maximum error in the proposed‐EFA and proposed‐FTFA designs to be not more than unit bit value with weights 2[(n/2m)−1]m and 2n/2, respectively. Two different FTFA cells are proposed and implemented in the approximate blocks. The synthesis results of the proposed‐EFA, proposed‐FTFA1 and proposed‐FTFA2 designs using Cadence Encounter with 90 nm ASIC technology for n = 16, m = 4 demonstrated an area saving of 22.3, 28.2 and 35%, respectively, when compared to the conventional counterpart.

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Section: Fpga Implementation In Digital Image Processingmentioning

confidence: 99%

Area‐efficient parallel adder with faithful approximation for image and signal processing applications

Palanisamy¹,

Natarajan²,

Sundaram³

2019

IET image process

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“…Experimentally, it has been found the efficiency of software implementation of HT is less than satisfactory, considering the number of data samples as well as implementation method, which demands for development of real time systems for implementation of HT [10]. There have been various algorithms implemented till now for the implementation of the HT such as implementation using Discrete Hartley Transform (DHT) [3], Implementation via Discrete Cosine Transform [11], and Implementation using Hilbert Transformer using Canonic Signed Digit coefficients [12]. The paper presents two novel architectures for implementation of HT using FFT.…”

Section: Daniel Rajumentioning

confidence: 99%

“…Therefore, the ratio of time has the significance, which describes the advantage of usage of FFT overDFT. System Generator is one of the leading industrial tools used for designing high performance DSP systems on FPGA [12]. Fig.3.…”

Section: Proposed Architecture For Htmentioning

confidence: 99%

Efficient architecture for real time implementation of Hilbert Transform in FPGA

Prince

Verma

Jayakumar

et al. 2015

2015 IEEE International Conference on Electrical, Computer and Communication Technologies (ICECCT)

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This paper presents an architecture for real time hardware implementation of Hilbert Transform (HT) using Fast Fourier Transform (FFT). HT is studied and its various application areas are discussed in the paper. Two different architectures are proposed using Fast Fourier Transform (FFT) for the implementation. Implementation of HT using the proposed FFT based architectures are compared with the implementations using Discrete Fourier Transform (DFT) and Discrete Hartley Transform (DHT). The proposed FFT based architectures are implemented on Xilinx Kintex-7 based FPGA and the results acquired are presented in comparison to results obtained through MATLAB simulations. The architecture implemented supports transform length of 8192 points as a demonstrator to the idea using 24 bit fixed point arithmetic.Detailed comparison study in terms of resource utilization and timing analysis is also carried out and the results are reported.

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“…1. Practical Hilbert filters does not have flat passband over the entire pass band [9,10,11,12]. Also, delay compensations are required in the other signal path to align Fig.…”

Section: Introductionmentioning

confidence: 99%

“…In digital platform, FPGAs are used to implement signal processing algorithms for communication applications [13,14,15] and it is a prototyping option for ASIC developments [16,17,18,19]. Hilbert FIR filter implementation on FPGA is presented in [9]. On the other hand, identical FIR filters which are matched in gain and having orthogonal phases are ideal for analytic signal generation as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Phase-orthogonal FIR filters: An efficient VLSI architecture for communication applications

Duraiswamy

Satishkumar

Raghu

et al. 2020

IEICE Electron. Express

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90 • phase shifters are used in various communication applications such as analytic signal (I and Q) generation, image rejection and Single Side Band (SSB) modulation. In this article, we present an efficient VLSI architecture for the generation of IQ signal with reduced amplitude and phase mismatches using phase-orthogonal FIR phase shifter. The proposed design and implementation reduces the constant multipliers in FIR filter from 2N to N /2 in two steps. In the first step, the filter passband is centered around 0.25fs which makes the alternate filter coefficients zero, reducing the multiplier count to N. In the second step, the hardware architecture is designed in such a way that the time-reversal property of the two filters is exploited to reduce further the multiplier count to N /2. A transposed FIR filter structure with Canonic Signed Digit(CSD) coefficients is adopted for implementation on FPGA. The dual filter approach and the optimization technique has resulted in better filter performance compared to the conventional Hilbert filter approach. The FPGA implementation gives a phase and amplitude ratio error of −0.17 • and 0.0002 dB for a filter order of 26 and −0.21 • and 0.0053 dB for a filter order of 32 respectively. Despite having two filters, the area increase is only 50% of widely used Hilbert transformer method that uses a single FIR filter. The designed phase shifter shifter is used to simulate an SSB modulator. A side band suppression of 18.9dB is achieved with the proposed phase-orthogonal phase shifter, which is ≈8 dB better than the Hilbert filter based SSB modulator.

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Efficient implementation of 90° phase shifter in FPGA

Cited by 12 publications

References 8 publications

Area‐efficient parallel adder with faithful approximation for image and signal processing applications

Area‐efficient parallel adder with faithful approximation for image and signal processing applications

Efficient architecture for real time implementation of Hilbert Transform in FPGA

Phase-orthogonal FIR filters: An efficient VLSI architecture for communication applications

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