Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters

Sung, Tze-Yun; Hsin, Hsi-Chin; Shieh, Yaw-Shih; Yu, Chun-Wang

doi:10.1109/pdcat.2006.78

Cited by 13 publications

(5 citation statements)

References 6 publications

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“…In particular, we separated the following works: [35,[60][61][62][63][64][65]. Table 4.9 are for the CSD representation considering 8-bit equivalent word size, unless it is specifically mentioned that we employed the expansion factor method.…”

Section: Fpga Implementation and Resultsmentioning

confidence: 99%

VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers

Madishetty

Madanayake

Cintra

et al. 2013

IEEE Trans. Circuits Syst. I

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Discrete wavelet transforms (DWTs) are of special interest in signal and image processing due to their capability of signal decomposition, denoising, and event detection. This thesis proposes a novel algebraic integer (AI) based multi-encoding of Daubechies-4 and-6 2-D wavelet filters having error-free integer-based computation. Digital VLSI architectures employing parallel channels are proposed, physically realized and tested. The multi-encoded AI framework allows a multiplication-free and computationally accurate architecture. It also guarantees a noise-free computation throughput the multi-level multi-rate 2-D filtering operation. A single final reconstruction step (FRS) furnishes filtered and down-sampled image outputs in fixed-point, resulting in low levels of quantization noise. Significant SNR and PSNR improvements were observed in favour of AIbased systems, when compared to 8-bit fixed-point schemes (six fractional bits). The designs are physically implemented for a 4-level 2-D decomposition using Daubechies-4 and-6 4-level VLSI architectures on a Xilinx Virtex-6 vcx240t-1ff1156 FPGA device and verified on an FPGA chip using an ML605 platform. A 45 nm CMOS synthesis shows improved clock frequencies for a supply voltage of 1.1 V.

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Section: Fpga Implementation and Resultsmentioning

confidence: 99%

VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers

Madishetty

Madanayake

Cintra

et al. 2013

IEEE Trans. Circuits Syst. I

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“…Tze-Yun et al [28] Marino et al [29] Mohanty et al [30] Madishetty et al [23] Wang et al [27] Wu et al [12] Meihua et al […”

Section: Perspectivesmentioning

confidence: 99%

FPGA Implementation of Ultra-High Speed and Configurable Architecture of Direct/Inverse Discrete Wavelet Packet Transform Using Shared Parallel FIR Filters

Chehaitly¹,

Tabaa²,

Monteiro³

et al. 2018

Adv. sci. technol. eng. syst. j.

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This work presents new pipeline-parallel, generic and configurable parallel hardware architectures for the Direct/Inverse Wavelet Packet Transform (DWPT/IDWPT) independent of any specific family of wavelets, implemented in FPGA technology using a parallel architecture of direct FIR filter. We propose in the following paper, new P-parallel structures for the DWPT and IDWPT transforms based on the Mallat binary tree algorithm. Therewith, we developed a P-parallel/modified direct FIR filter architecture using pipelineparallelize and hardware resource sharing, which provides not only ultra-high speed data processing but also a limited amount of hardware as resources are shared between filters and the bidirectional wavelet packet transformation. This model follows two important strategies: I) a powerful structure pipeline/P-parallel using strict data management and interleaving, II) sharing hardware at different levels in the transformation and between the two DWPT/IDWPT transformations. These architectures are modeled in VHDL at RTL modeling level. They are generic and fully configurable: at synthesis and post-synthesis. The simulation results show an acceleration of data processing to an approximate value of P-Parallel multiplied by frequency with lower used resources. Furthermore, the impact of tree depth and filters order on throughput is very light due to the linearize architecture of our model. The synthesis was achieved using the Intel Quartus Prime Lite Edition software and targeting the Intel Altera Cyclone FPGA technology.

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“…In high speed or low-power image processing applications, require a computationally simplified and memory efficient algorithm. Recently, a new mathematical formulation for wavelet transformation has been proposed in [3] as a light-weighted computation method for performing wavelet transforms with low power techniques. The liftingbased wavelet transform break-up the high pass and the low pass wavelet filters into a sequence of smaller filters.…”

Section: Proposed Maesmentioning

confidence: 99%

Hardware Implementation of Modified AES Algorithm for Secure Images

Rabid¹,

Jithesh²

2017

IJERT

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Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters

Cited by 13 publications

References 6 publications

VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers

VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers

FPGA Implementation of Ultra-High Speed and Configurable Architecture of Direct/Inverse Discrete Wavelet Packet Transform Using Shared Parallel FIR Filters

Hardware Implementation of Modified AES Algorithm for Secure Images

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