Low-power multiplierless DCT architecture using image correlation

Jeong, Hyuntae; J, Kim; Cho, Won-kyung

doi:10.1109/tce.2004.1277872

Cited by 63 publications

(5 citation statements)

References 8 publications

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“…The fixed-rotation ACor happened when the input angle of z 0 is known. Fixed-rotation ACor implementations were common in CORDIC-based DCT SFGs [14,15,24]. With the known z 0 -value, the iteration process of the z j becomes a pre-determination process.…”

Section: The Fixed-rotation Implementationmentioning

confidence: 99%

“…The worthmentioned works were the BinDCT of J. Liang and T. D. Tran in 2001 [8], approximate DCT of M. Parfieniuk et al in 2013 [9], integer DCT of P. K. Meher et al in 2014 [10], scalable orthogonal approximation DCT of M. Jridi et al in 2015 [11], adaptive approximate DCT of M. Masera et al in 2016 [12], and optimized real-valued DCT of S. Chatterjee and K. Sarawadekar in 2018 [13]. Besides the above methods, the COordinate Rotation DIgital Computer (CORDIC) approach was also among the well-known ways to create a high-speed DCT SFG, and several CORDICbased DCT implementations had been proposed lately [14,15,16,17]. The idea of Adaptive CORDIC (ACor) was first introduced by Y. H. Hu and S. Naganathan in 1993 [18] to reduce the number of iteration step.…”

Section: Introductionmentioning

confidence: 99%

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A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC

Hoang

Pham

2019

IEICE Electron. Express

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In this paper, a Silicon On Thin Buried-oxide (SOTB) implementation of a 32-point Discrete Cosine Transform (DCT) is presented. The architecture is based on the fixed-rotation adaptive COordinate Rotation DIgital Computer (CORDIC) algorithm. The SOTB-65 nm process was chosen due to the profound advantages of low-power and highperformance. The core layout contained about 47.2 K gate-count and had the size of about 183 K-µm 2. The measurement results showed that the highest operating frequency of 62-MHz was achieved at the 1.05-V power supply and consumed about 737-µW and 11.89-pJ/cycle. In the standby mode, the least power consumption of 0.12-nW was achieved at the 0.4-V power supply when the clock-gating technique and −2.5-V reverse backgate biassing were applied.

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Section: The Fixed-rotation Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC

Hoang

Pham

2019

IEICE Electron. Express

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“…There are many CORDIC-based DCT designs had been proposed lately [11][12][13]. The CORDICbased DCT architecture can be seen as an approximation implementation.…”

Section: Introductionmentioning

confidence: 99%

Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC

Hoang

Pham

2018

IEICE Electron. Express

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In this paper, the minimum adder-delay Discrete Cosine Transform (DCT) architecture is proposed using the Adaptive CORDIC (ACor) algorithm with fixed-rotation implementations. The proposed method has six different versions differ from the number of DCT point, i.e., 8-point (8p), 16-point (16p), and 32-point (32p), and the number of ACor stages, i.e., 2-Stage (2S) and 3-Stage (3S). The Altera Stratix IV and Stratix II FPGAs were used to built and verified the implementations. The 2S designs of 8p, 16p, and 32p DCT achieved the timing performances of four, five, and six adder-delay results, respectively. The proposed method was proven to have the best timing performances, good accuracy results, and adequate resources cost in comparison with other recent works.

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“…The technique which uses Ramanujan numbers for calculating cosine values and uses Chebyshev type recursion to compute DCT [12] was also proposed. A low power multiplier-less DCT was presented in [13], and it reduces the switching power consumption around 26 % by removing unnecessary arithmetic operations on unused bits during the CORDlC calculations. The complexity of DCT computation was reduced in [14] by optimizing the Loeffler DCT, based on the CORDlC algorithm.…”

Section: Introductionmentioning

confidence: 99%

Implementation of computation-reduced DCT using a novel method

Senthilkumar

Kunaraj²,

Seshasayanan

2015

J Image Video Proc.

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The discrete cosine transform (DCT) performs a very important role in the application of lossy compression for representing the pixel values of an image using lesser number of coefficients. Recently, many algorithms have been devised to compute DCT. In the initial stage of image compression, the image is generally subdivided into smaller subblocks, and these subblocks are converted into DCT coefficients. In this paper, we present a novel DCT architecture that reduces the power consumption by decreasing the computational complexity based on the correlation between two successive rows. The unwanted forward DCT computations in each 8 × 8 sub-image are eliminated, thereby making a significant reduction of forward DCT computation for the whole image. This algorithm is verified with various high-and less-correlated images, and the result shows that image quality is not much affected when only the most significant 4 bits per pixel are considered for row comparison. The proposed architecture is synthesized using Cadence SoC Encounter® with TSMC 180 nm standard cell library. This architecture consumes 1.257 mW power instead of 8.027 mW when the pixels of two rows have very less difference. The experimental result shows that the proposed DCT architecture reduces the average power consumption by 50.02 % and the total processing time by 61.4 % for high-correlated images. For less-correlated images, the reduction in power consumption and the total processing time is 23.63 and 35 %, respectively.

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Low-power multiplierless DCT architecture using image correlation

Cited by 63 publications

References 8 publications

A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC

A 1.05-V 62-MHz with 0.12-nW standby power SOTB-65 nm chip of 32-point DCT based on adaptive CORDIC

Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC

Implementation of computation-reduced DCT using a novel method

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