Low power SAR ADC switching without the need of precise second reference

Osipov, Dmitry; Paul, Steffen

doi:10.1007/s10470-018-1225-2

Cited by 10 publications

(6 citation statements)

References 21 publications

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“…Tese schemes include the two-level, three-level and four-level voltage switching schemes. Two-level voltage switching schemes have been used in [41,44,57,[69][70][71][72][73] to improve the power consumption and enhance the stability and accuracy of CDAC. Higher precision and linearity can be obtained with lower average switching energy by employing two-level voltages.…”

Section: Cdac Voltage Switching Schemesmentioning

confidence: 99%

“…Te negative side of this scheme is the efect of capacitor mismatch on the linearity and also, the number of clock cycles will increase with the number of bits. Te DC-DC converter is utilized in [72,73]. Te two steps down DC-DC…”

Section: Cdac Voltage Switching Schemesmentioning

confidence: 99%

“…Mainly, two parameters have been utilized to achieve power consumption reduction: decreasing the size of the capacitor array and using diferent level voltages. Te Scaled down reference [33] Scaled down reference [36] Monotonic [18] Monotonic [40] Charge redistribution [60] Two-step switching method [63] Charge sharing [22] Tri-level [65] Vcm-based [66] Hybrid [70] Hybrid [35] HSRS [73] Two energy saving [71] HSRS [76] Vaq-based [79] Vaq-based [31] Switching CDAC is suitable for the low-power SAR ADC. However, the diferent voltage switching schemes can improve the switching power consumption.…”

Section: Fom W � P Adcmentioning

confidence: 99%

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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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Section: Cdac Voltage Switching Schemesmentioning

confidence: 99%

Section: Cdac Voltage Switching Schemesmentioning

confidence: 99%

Section: Fom W � P Adcmentioning

confidence: 99%

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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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“…6. The simulation is done without and with mismatch by considering 1 % unit capacitor mismatch [27], [28]. The simulation result for proposed CDAC is shown in Fig.…”

Section: Circuit Implementation a Capacitive Dacmentioning

confidence: 99%

A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications

et al. 2020

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An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications. An improved common mode charge redistribution algorithm is proposed for binary weighted SAR ADC. The proposed method uses available common mode voltage (V CM) level for SAR ADC conversion, and this method reduces the switching power by more than 12% without any additional DAC driver as compared to merged capacitor switching (MCS). Mathematical analysis of the proposed switching scheme results in the lower or equal power consumption for every digital code as compared to MCS. A two stage dynamic latched comparator with adaptive power control (APC) technique is used to optimize the overall efficiency. Furthermore, to minimize the digital part power consumption, a modified asynchronous SAR logic with digitally controlled delay cells is proposed. High efficiency with low power consumption makes it suitable for low power devices especially for IEEE 802.15.1 IoT sensor based applications. The proposed prototype is implemented using 1P6M 55 nm complementary metal-oxide-semiconductor (CMOS) technology. The measurement results that the proposed circuit achieves are 9.3 effective number of bits (ENOB) with signal-to-noise and distortion ratio (SNDR) of 58.05 dB at a sampling rate of 8 MS/s. The power consumption of SAR ADC is 45 µW when operated at 1 V power supply. INDEX TERMS Adaptive power control (APC), asynchronous logic, Bluetooth low energy (BLE), capacitive DAC (CDAC), IEEE 802.15.1 IoT sensors, low power consumption, successive approximation register (SAR) ADC.

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“…The implementation of high-speed ADC as a bulding block of readout ASICs in CMOS processes of technology nodes 130-180 nm results in high power consumption and large chip area. For known ADCs working with sampling rate more than 100 MHz the power consumption still reaches tens of mW [1][2][3][4] despite of the application of new architectural solutions [5]. That is inappropriate application for a low-power design of multichannel read-out ASICs.…”

Section: Introductionmentioning

confidence: 99%

Implementation of the interpolator for signal peak detection in read-out ASIC

Shumikhin¹,

Azarov²,

Bulbakov³

et al. 2020

J. Inst.

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A: A prototype interpolator for signal peak detection in read-out ASIC is presented. It uses interpolation algorithm for finding additional points between ADC samples. This allows to increase an accuracy for signal peak detection. Behavioral models of interpolator for Spline and Lagrange algorithm were realized and compared. Interpolator was designed in 180 nm UMC MMRF CMOS process. It is based on a 6th order Lagrange interpolation polynomial. The interpolator ensures the accuracy of signal peak finding is less than 1.5 LSB of ADC at sampling frequency of 25 MHz and 200 ns peaking time of 2nd order shaper.

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Low power SAR ADC switching without the need of precise second reference

Cited by 10 publications

References 21 publications

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications

Implementation of the interpolator for signal peak detection in read-out ASIC

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