Low-Power Soft Error Hardened Latch

Alidash, Hossein Karimiyan; Oklobdzija, Vojin G.

doi:10.1166/jolpe.2010.1073

Cited by 22 publications

(24 citation statements)

References 0 publications

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“…This section reviews DET-SEHPL latch [15], latch design in [12] (hereinafter referred to as NAN1 latch), HLR latch [6], latch design in [9,10] (hereinafter referred to as LCHR latch, and NAN2 latch, respectively), FERST latch (the enhanced version) [16], and LSEH1/LSEH2 latch [8].…”

Section: Previous Hardened Latchesmentioning

confidence: 99%

“…Usually, SET generates from preceding combinational path, in which, timing overhead should also be considered when hardening, thus SET hardening is more complex than SEU hardening in integrated circuits and systems, and recently, researchers considered both SEU and SET hardening in latches. Using Radiation Hardening by Design (RHBD) technique, a number of hardened latches devoted by researchers that presented a very important contribution to SE mitigation have been proposed in the literature [2,[4][5][6][7][8][9][10][11][12][13][14][15][16][17]. These schemes make use of spatial and/or temporal redundancy for hardening, and we can classify them into four different categories similar to references [8,9]: 1) Latches being not fully SEU immune [2,7,15], i.e.…”

Section: Introductionmentioning

confidence: 99%

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An SEU resilient, SET filterable and cost effective latch in presence of PVT variations

Yan

Liang²,

Huang³

et al. 2016

Microelectronics Reliability

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Section: Previous Hardened Latchesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations

Yan

Liang²,

Huang³

et al. 2016

Microelectronics Reliability

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“…Recently, many schemes about latch hardening against SET or SEU have been proposed [3,4,5,6,7,8,9, 10] and these schemes could be divided into three categories: 1) SEU not immune ones [3,4], i.e. there is at least one weak node and if the node is flipped by an SEU the latch would retain invalid data; 2) SEU immune but SET not filterable ones [5,6,7,8], i.e.…”

Section: Introductionmentioning

confidence: 99%

“…Fig. 2 has presented a typical SEU-not-immune latch [4]. In latching mode of operation, if Q is affected by an SEU, the latch would retain invalid data, since Q is feeding back to nodes N1 and N2 simultaneously.…”

Section: Introductionmentioning

confidence: 99%

A transient pulse dually filterable and online self-recoverable latch

Yan

Liang

et al. 2017

IEICE Electron. Express

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This paper presents a transient Pulse Dually Filterable and online Self-Recoverable (referred to as PDFSR) latch. Based on soft error masking property of C-element and using built-in delayed paths combined with a Schmitt inverter, a single event transient (SET) pulse could be dually filtered. Meanwhile, mutually feeding back mechanism of multiple C-elements was constructed to retain data, which makes the latch self-recoverable from a single event upset (SEU). Simulation results have demonstrated the SET filtering ability and SEU resilience at the cost of only 2.0% area-powerdelay-width product increase on average, compared with the similar latches.

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“…The area overhead is huge as three FFs are used. In case of glitch filtering, the glitch generated due to SET is filtered by delaying the data path [15]. The major difference between majority voting or glitch filtering and our work is that majority voting and glitch filtering are used for error correction whereas the proposed FF is used for warning detection.…”

Section: Introductionmentioning

confidence: 99%

Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs

Das

Onodera

2014

IEEE Trans. VLSI Syst.

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In this paper, a metastability immune warning flipflop (FF) is proposed which consists of an edge detector, a warning window generator and a warning detector along with a traditional FF. The delayed data is monitored during the warning window to flag a warning signal before the data enters the erroneous zone. In this scheme, the warning window is independent of input clock frequency and hence is suitable for frequency scaling application. A 16-bit Kogge-stone adder is implemented in 65 nm technology which uses warning FF for dynamic voltage and frequency scaling (DVFS). The warning FF based DVFS allows elimination of safety margins and operates till the point of first warning of the adder without any erroneous results. Experiments were conducted with different supply voltages, phase-shifted clocks and process conditions. The circuit is helpful to determine when to stop further reduction in supply voltage by producing the warning signal with pre-defined timing slacks in DVFS application. The test chip results demonstrate that the proposed circuit can track the critical path delay of 2.4 ns to 7.5 ns at warning voltage of 1.15 V to 0.72 V respectively. The measured results from 10 different chips show effectiveness of the proposed concept across process variation.

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Low-Power Soft Error Hardened Latch

Cited by 22 publications

References 0 publications

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations

A transient pulse dually filterable and online self-recoverable latch

Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs

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