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Configurable electronic devices have been developed to provide more flexibility in the advanced digital system design, which needs more device density and there by relies on device scaling. Besides, International Technology Roadmap for Semiconductor (ITRS) has predicted scaling limitation for conventional silicon (Si)-based devices. Researches on post-Si materials have proved that carbon could be one of the material which can replaced with Si. Owing to exceptional properties of graphene, designs with graphene-based devices can replace with Si based ones. This study proposes design and characterisation of graphene-based simple field-programmable gate array as a platform of configurable logic structure for future developments. This study focuses on design and characterisation of configurable logic block (CLB), flip-flop as internal sequential logic devices in CLB, and routing switch, which are designed using graphene nanoribbon field-effect transistor (GNRFET). The results indicate that proposed CLB is much faster than Si based one and power-delay product of proposed sequential element is much lesser than its counterpart in Si-based technology. In addition, the proposed GNRFET-based routing switch requires minimum count of 6 transistors to provide desirable functionality. Foreseeing the feasibility of architecture, this study suggests the possible layout of the proposed logic elements needed for CLB.

GNRFET Graphene Nano-Ribbon Field-Effect Transistor is sensitive to geometric parameters. Therefore, changing parameters circuit characteristics can be improved or degraded. In this study, we propose a new approach to optimizing the GNRFETs. The effect of geometric and process parameters such as chirality, channel length, width, line edge roughness, oxide thickness, and doping on characteristics of an inverter gate is investigated based on GNRFET. Analysis of power consumption, delay, PDP, and SNM results indicate that GNRFETs adjustable parameters can significantly affect circuit performance. It is shown that SNM increases by changing channel length and width. Moreover, by reducing the channel length from 20 nm to 10 nm, delay for chirality (6,0) decreases by 50%, and delay for chirality (10,0) decreases by 53%. By increasing the Line Edge Roughness by 20%, power consumption for chirality (10,0) and chirality (6,0) increases by 18% and exponentially, respectively. Also, by decreasing the oxide thickness, SNM and power consumption are increased; however, the delay behaves differently with chiralities (6,0) and (10,0). This research demonstrates the importance of accurately determining the GNRFET adjustable parameters according to the design aims. A set of recommendations is provided for optimal parameters needed by digital circuit designers to use GNRFET in their design optimally.

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