Low power strategy about correlator array for CDMA baseband processor

Ku, Chung-Wei; Kuo, Fu-Yen; Chen, Chi-Kuang; Chen, Liang-Gee

doi:10.1109/sips.1999.822357

Cited by 2 publications

References 7 publications

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A digital signal processor with programmable correlator array architecture for third generation wireless communication system

Chen¹,

Tseng²,

Chang³

et al. 2001

IEEE Trans. Circuits Syst. II

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In this paper, a digital signal processor (DSP) with programmable correlator array architecture is presented for third generation wireless communication system. The programmable correlator array can be reconfigured as a chip match filter, code group detector, scrambling code detector, and RAKE receiver with low power consideration. The architecture and instruction set of the proposed DSP are specially designed for several key operations of wireless communications, such as channel estimation for RAKE combining, Viterbi algorithm and finite-impulse response filtering. According to the performance evaluation results, the proposed DSP outperforms other previously presented communication digital signal processors in terms of several crucial operations of wireless applications. A chip of the proposed DSP was implemented using hybrid design method where the timing critical components were full-custom designed and the other parts were cell-based designed under TSMC 0.35-m CMOS 1P4M technology. We believe that the proposed system architecture would be useful for upcoming 3G mobile terminal applications.

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