Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment

Chang, Yen-Jen; Tsai, Kun-Lin; Cheng, Yu-Cheng; Lu, Meng-Rong

doi:10.1016/j.compeleceng.2019.106528

Cited by 6 publications

(7 citation statements)

References 9 publications

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“…The mask bit "5th" compares all cells in the last column in parallel; in which, two cells "0" and "31" are shown, as described about 8 nW, which is usually very small due to the small size of the memory array 32-bit X 6-bit. The static power usually has a side effect for a memory array in the order of Mega-to-Giga sizes, 14,16 and thus, the static power is ignored.…”

Section: Operating Voltagementioning

confidence: 99%

“…13,14 Other recent works leverage the benefit of the SRAM-based CAM structure to maintain multiple operations for the cost of low-speed and low memory scalability. 15,16 Conventionally, the CAM structure comprises several cycles to scan all content of memory tables and releases the matched row index obviating comparators/encoders for the cost of reducing throughput by introducing several execution cycles. 17,18 Another essential factor in the memory array table is the type of the memory cell structure.…”

Section: Introductionmentioning

confidence: 99%

“…Subsequently, the proposed CAM operation compares all memory rows against the mask data in parallel and releases the matched row indexed within one cycle obviating extra latency cycles and wide comparators as in counterpart CAM designs. 16,17 In conclusion, the proposed Alias Table circuitry summarized the following key features: The remainder of this paper is organized as follows. Section 2 discusses the design of the SRAM-based CAM cell circuit structure.…”

Section: Introductionmentioning

confidence: 99%

“…Consequently, some RRU tables realize SRAM‐based rather than CAM‐based implementations for more memory layout scalability and high‐speed at the cost of extra overhead comparators/encoders and few latency cycles 13,14 . Other recent works leverage the benefit of the SRAM‐based CAM structure to maintain multiple operations for the cost of low‐speed and low memory scalability 15,16 . Conventionally, the CAM structure comprises several cycles to scan all content of memory tables and releases the matched row index obviating comparators/encoders for the cost of reducing throughput by introducing several execution cycles 17,18 …”

Section: Introductionmentioning

confidence: 99%

“…Thus, if all cells in a particular row match the data of the mask register, the match line for that particular row preserves the pre‐charged power supply value, thus enabling the Tri‐state buffer to release the row index to the output match port. Subsequently, the proposed CAM operation compares all memory rows against the mask data in parallel and releases the matched row indexed within one cycle obviating extra latency cycles and wide comparators as in counterpart CAM designs 16,17 …”

Section: Introductionmentioning

confidence: 99%

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Design of memory Alias Table based on the SRAM 8T‐Cell

Abdel‐hafeez

Otoom

Quwaider

2022

Circuit Theory & Apps

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A memory Alias Table holds a major role in Register Renaming Unit (RRU), which is responsible for maintaining the translation between logical registers to physical registers under the given instruction(s). This work presents the design of the memory Alias Table based on the SRAM‐based 8T‐Cell with multiport write, read, and content‐address operations for two‐way three operands machine cycle. The design of the memory Alias Table of size 32‐row × 6‐bit has SRAM‐based CAM cell of type 21T‐Cell that comprises four‐read ports, two‐write ports, and two‐content‐address ports. The content‐address examines the register under‐test against all contents of the memory Alias Table in parallel and releases the associated match index address. Results show that the four read ports operate simultaneously within the half‐cycle, while the two write ports operate simultaneously within the other half‐cycle. The operation of the two content‐address ports is managed during the half‐cycle of the read phase. Thus, the three operations occur within a single cycle without latency. HSPICE simulations using 90 nm/1 V CMOS process reveal that the memory Alias Table provides the three operations within a one‐cycle of 1 GHz consuming an average power of 0.13 mW.

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Section: Operating Voltagementioning

confidence: 99%