No abstract

A memory Alias Table holds a major role in Register Renaming Unit (RRU), which is responsible for maintaining the translation between logical registers to physical registers under the given instruction(s). This work presents the design of the memory Alias Table based on the SRAM‐based 8T‐Cell with multiport write, read, and content‐address operations for two‐way three operands machine cycle. The design of the memory Alias Table of size 32‐row × 6‐bit has SRAM‐based CAM cell of type 21T‐Cell that comprises four‐read ports, two‐write ports, and two‐content‐address ports. The content‐address examines the register under‐test against all contents of the memory Alias Table in parallel and releases the associated match index address. Results show that the four read ports operate simultaneously within the half‐cycle, while the two write ports operate simultaneously within the other half‐cycle. The operation of the two content‐address ports is managed during the half‐cycle of the read phase. Thus, the three operations occur within a single cycle without latency. HSPICE simulations using 90 nm/1 V CMOS process reveal that the memory Alias Table provides the three operations within a one‐cycle of 1 GHz consuming an average power of 0.13 mW.

Memory Alias Table exploits a major role in Register Renaming Unit (RRU) for maintaining the translation between logical registers to physical registers for the given instruction(s). This work presents the design of the memory Alias Table based on the 8TCell with multiport write, read, and content-addressable operation for 2-WAY three operands machine cycle. Results show that four read ports operate simultaneously within a half-cycle, while two-write ports operate simultaneously within the other half-cycle. The operation of content-addressable with two parallel ports is managed during the half-cycle of the read phase; thus, the three operations occur within a single cycle without latency. HSPICE simulations conduct 32-rows x 6-bit with 21T-Cell memory Alias Table that has 4- read ports, 2-write ports, and 2-content-addressable ports using a standard 65 nm/1V CMOS process. Simulations reveal that the proposed design operates within a one-cycle of 1 GHz consuming an average power of 0.87 mW