Low-quantum cost circuit constructions for adder and symmetric Boolean functions

Chattopadhyay, Anupam; Baksi, Anubhab

doi:10.1109/iscas.2016.7539042

Cited by 3 publications

(5 citation statements)

References 18 publications

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“…Four commonly used reversible logic realisation parameters are QC, GC. AI and GO [16] - [27]. Quantum Cost (QC)refers to the number of primitive quantum gates in the circuit.…”

Section: B 2-bit Gatesmentioning

confidence: 99%

“…Realisation of circuits and systems using reversible logic gates is an emerging area of research. The efficacy of circuit realisations using reversible logic is measured in scales of one or a combination of reversible logic realisation parameters -QC, GC, GO and AI [16] - [27].…”

Section: Introductionmentioning

confidence: 99%

“…Chattopadhyay and Baksi [16] proposed two low quantum cost circuit construction for symmetric Boolean functions. The authors have demonstrated the implementation of adder circuits and has measured and compared the efficacy of the proposed adder by projecting GO, GC, and QC.…”

Section: Introductionmentioning

confidence: 99%

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Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic

et al. 2021

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This paper proposes an inexact Baugh-Wooley Wallace tree multiplier with novel architecture for inexact 4 : 2 compressor optimised for realisation using reversible logic. The proposed inexact 4 : 2 compressor has ±1 Error Distance (ED) and 12.5% Error Rate (ER). The efficacy of the proposed reversible logic based realisation of the proposed inexact 4 : 2 compressor and Baugh-Wooley Wallace tree multiplier is measured in scales of Gate Count (GC), Quantum Cost (QC), Garbage Output (GO) and Ancilla Input (AI). The proposed inexact 4 : 2 compressor is able to reduce reversible logic realisation metrics GC, QC, GO and AI by 50%, 15%, 25% and 11.11% as compared to reversible logic realisation of exact 4 : 2 compressor. An 8 × 8 Baugh-Wooley Wallace tree multiplier is implemented in this paper and is utilised in two applications 1) image processing -one level decomposition using rationalised db6 wavelet filter bank and image smoothing and 2) Convolutional Neural Networks (CNN). The efficacy of the proposed multiplier in image processing applications is estimated by measuring Structural Similarity Index Measure (SSIM) which is found to be 0.96 and 0.84 for image decomposition and smoothing respectively. In CNN based application, the efficiency is measured in scales of accuracy and is found to be 97.1%.

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“…Four commonly used reversible logic realisation parameters are QC, GC. AI and GO [16] - [27]. Quantum Cost (QC)refers to the number of primitive quantum gates in the circuit.…”

Section: B 2-bit Gatesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic

et al. 2021

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“…The Peres' implemented Ful Adder with its corresponding quantum cost can be seen below: ible logic implementation of full-adder circuit and other adder circuits and their minimization issues has been discussed in . It has been shown in [11] and [13] that any reversible logic realization of full adder circuit includes at least two garbage outputs and one constant input. The author in [10][11][12][13] has given a quantum cost efficient reversible full adder circuit that is realized using two 3*3 Peres gates only (shown in figure 3.1).…”

Section: Introductionmentioning

confidence: 99%

“…It has been shown in [11] and [13] that any reversible logic realization of full adder circuit includes at least two garbage outputs and one constant input. The author in [10][11][12][13] has given a quantum cost efficient reversible full adder circuit that is realized using two 3*3 Peres gates only (shown in figure 3.1). This implementation of reversible full adder circuit is also efficient in terms of gate count, garbage outputs and constant input than For this implementation, I will be using the Peres gate as it is the gate with the lower quantum cost as can be seen in the figures 3.1.…”

Section: Introductionmentioning

confidence: 99%

A Design and Implementation of Reversible Logic Based Combinational Circuit with low Quantum Cost

Jain¹,

Raghuwanshi²

2017

IJTSRD

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In the field of cryptography, optical information processing low power CMOS design and nanotechnology Reversible logic has found its applications and has become one of the promising research directions this paper presents a novel and quantum cost efficient combinational circuits for nanotechnology. This gate can work singly as a reversible full adder unit and requires only one clock cycle. The proposed gate is a universal gate in the sense that it can be used to synthesize any arbitrary Boolean functions. It has been demonstrated that the hardware complexity offered by the proposed gate is less than the existing counterparts. The proposed reversible circuits are then compared with different reversible circuits

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