2006
DOI: 10.1016/j.sse.2006.03.036
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Low temperature characterization of effective mobility in uniaxially and biaxially strained nMOSFETs

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Cited by 19 publications
(3 citation statements)
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“…At the same time, a strong enhancement in performance of CMOS devices can be achieved by introducing strain-engineering techniques without adding major process complexity [5,6]. In [7], two categories of strain techniques have been distinguished: biaxial global strain, where stress is introduced across the whole wafer by epitaxial growth of a SiGe 'buffer layer' on top of the silicon substrate; and uniaxial local strain, based on the use of compressively strained (pMOS) or tensile (nMOS) dielectric layers (referred to as contact etch stop layer (CESL)) which are directly deposited around the gate after frond-end-ofline processing to give a stress along the channel.…”
Section: Introductionmentioning
confidence: 99%
“…At the same time, a strong enhancement in performance of CMOS devices can be achieved by introducing strain-engineering techniques without adding major process complexity [5,6]. In [7], two categories of strain techniques have been distinguished: biaxial global strain, where stress is introduced across the whole wafer by epitaxial growth of a SiGe 'buffer layer' on top of the silicon substrate; and uniaxial local strain, based on the use of compressively strained (pMOS) or tensile (nMOS) dielectric layers (referred to as contact etch stop layer (CESL)) which are directly deposited around the gate after frond-end-ofline processing to give a stress along the channel.…”
Section: Introductionmentioning
confidence: 99%
“…Comparing the material, diodes and FPA performances with the theoretical analysis on the thermal stress, it can be seen that the changes of the performance are related to the stress variation in the HgCdTe film as the material, diodes and FPAs' structures change. By using the energy band theory [7][8][9], an energy band under different thermal stress in HgCdTe along the carrier's motion way can be easily obtained.…”
Section: Discussionmentioning
confidence: 99%
“…With the introduction of strain, however, the energy of the valleys along the axis of the strain are raised while the energies of the valleys perpendicular to it are lowered. [75] There have been many papers calculating the Hamiltonian of an electron in a strained semiconductor. [76,77] The discussion in this section, which follows the work done by Pryor in his dotcode, follows work by Bahder.…”
Section: I52 Calculating With Strain In the K • P Methodsmentioning
confidence: 99%