Low-temperature CMOS-a brief preview

Abstract

Device improvements obtained from exploiting the dependence of physical characteristics of silicon at low temperature are above and beyond those improvements obtained from the usual geometric scaling of device dimensions. As device geometries continue to shrink into the deep submicrometer regime, second-order effects begin to limit further increases in device speed from scaling alone. Temperature scaling provides an additional variable for system optimization. The'gain in performance at cryogenic temperatures, however, is at the expense of inconvenience and additional cost for system refrigeration, and of increased susceptibility to hot-carrier degradation. Optimizing CMOS technology and design for low-temperature applications can increase performance and reduce power dissipation without increasing hot-carrier degradation.

Device Physics and Electrical Performance of Bulk Silicon Mosfets

“…The temperature reduction allows a substantial increase of the carrier mobility and saturation velo city, better turn-on capabilities, latch-up immunity, reduction in activated degradation processes, lower power consumption, decrease of leakage current, reduced thermal noise, increased thermal conductivity, etc [1][2][3][4][5][6][7][8][9][10][11][12]. Nevertheless, the low temperature operation leads to some problems and difficulties related to specific cryogenic conditions.…”