An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays: Digital and Analog Figures of Merit from 300K to 10K

Rosca, Teodor; Saeidi, Ali; Memišević, Elvedin; Wernersson, Lars‐Erik; Ionescu, Adrian M.

doi:10.1109/iedm.2018.8614665

Cited by 12 publications

(10 citation statements)

References 6 publications

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“…However, the difficulties of obtaining sufficiently sharp doping profiles or material interfaces pose incredible challenges to the realization of tunneling switches exploiting conventional three-dimensional semiconductors. Indeed, band-tail states and trap assisted tunneling paths can drastically degrade the turn-on slope of such devices 10,11 .…”

Section: Introductionmentioning

confidence: 99%

WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

et al. 2020

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Two-dimensional/two-dimensional (2D/2D) heterojunctions form one of the most versatile technological solutions for building tunneling field effect transistors because of the sharp and potentially clean interfaces resulting from van der Waals assembly. Several evidences of room temperature band-to-band tunneling (BTBT) have been recently reported, but only few tunneling devices have been proven to break the Boltzmann limit of the minimum subthreshold slope, 60 mV per decade at 300 K. Here, we report the fabrication and characterization of a vertical p-type Tunnel FET (TFET) co-integrated on the same flake with a p-type MOSFET in a WSe2/SnSe2 material system platform. Due to the selected beneficial band alignment and to a van der Waals device architecture having an excellent heterostructure 2D–2D interface, the reported tunneling devices have a sub-thermionic point swing, reaching a value of 35 mV per decade, while maintaining excellent ON/OFF current ratio in excess of 105 at VDS = 500 mV. The TFET characteristics are directly compared with the ones of a WSe2 MOSFET realized on the very same flake used in the heterojunction. The tunneling device clearly outperforms the 2D MOSFET in the subthreshold region, crossing its characteristic over several orders of magnitude of the output current and providing better digital and analog figures of merit.

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Section: Introductionmentioning

confidence: 99%

WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

et al. 2020

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“…In addition, TFETs' characteristics are susceptible to the trap-assisted tunneling (TAT), which will deterioratethe subthreshold behavior [10], [11]. The low temperature study is an effective tool to analyze the TAT and BTBT process [12], and can demonstrate that TFETs have attractive potential for medium and deep cryogenic operation like quantum computing and highly sensitive charge sensing [13], [14]. While CMOS circuitry experiences the performance degradation such as the dopant deactivation, carrier freeze-out and kinks in the transistor's output characteristics at the extreme low temperature (sub-20 K range) [14], [15].…”

Section: Introductionmentioning

confidence: 99%

“…The low temperature study is an effective tool to analyze the TAT and BTBT process [12], and can demonstrate that TFETs have attractive potential for medium and deep cryogenic operation like quantum computing and highly sensitive charge sensing [13], [14]. While CMOS circuitry experiences the performance degradation such as the dopant deactivation, carrier freeze-out and kinks in the transistor's output characteristics at the extreme low temperature (sub-20 K range) [14], [15]. Furthermore, the subthreshold slope property of TFETs has little dependence on the temperature since their BTBT conduction mechanisms [14].…”

Section: Introductionmentioning

confidence: 99%

“…While CMOS circuitry experiences the performance degradation such as the dopant deactivation, carrier freeze-out and kinks in the transistor's output characteristics at the extreme low temperature (sub-20 K range) [14], [15]. Furthermore, the subthreshold slope property of TFETs has little dependence on the temperature since their BTBT conduction mechanisms [14].…”

Section: Introductionmentioning

confidence: 99%

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Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current

Cheng

Liang

et al. 2020

IEEE J. Electron Devices Soc.

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In this paper, an N-type silicon line tunneling TFET (LT-TFET) with an ultra-shallow N + pocket was proposed. The pocket was formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy implantation and spike annealing. Due to the Ge PAI, the tunneling probability was improved significantly. As a result, a high on-state current of 40µA/µm, a minimum subthreshold swing (SS) of 69 mV/decade and an average SS of 80 mV/decade over 5 decades of drain current were achieved with V DS = V GS = 1 V at room temperature. It is shown that once the trap assisted tunneling is suppressedat the low temperature, the band-to-band tunneling becomes dominant. When the temperature decreases from 300 K to 4.9 K, the on-state current only reduces 20% and a minimumpoint SS of 10 mV/decadewas obtained. The LT-TFET exhibits improved transconductance efficiency at deep cryogenic temperature range. The proposed structure in this work shows attractive merits in the cryogenic digital and analog application. INDEX TERMS TFET Ge PAI, line tunneling, cryogenic temperature.

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“…The derivative of symmetric case potential distribution function w.r. Based on kane's method calculate tunnelingcurrent (ID) [26] which is done by assimilating the BTB generation rate of carriers (GBTB) [27] on the device volume. In this model we using BTB approach.…”

Section: Research Articlementioning

confidence: 99%

3D Analytical Modeling Of Surface Potential And Threshold Voltage Model Of Dm Fintfet With Dual Hetero Gate Oxide Structure

Dharmireddy¹

2021

TURCOMAT

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This paper proposed on basis of a perimeter-weighted-sum method for the construction of a 3D-Analytical Modeling of double metalFin structure TFET with dual hetero gate oxide structure. The DM model device dividing into a symmetrical and asymmetrical dual-gate TFETs, and then resolving 3D architectures. The surface potential and the electrical field (E) achieved by resolving the Poisson 3D equation. The drain current (ID) is eventually calculated using Kane tunneling model to calculate the tunneling generation rate. Threshold voltage model also developed based on the charge inversion model. The performance analysis of dual hetero gate oxide Fin TFET device together with dual dielectric engineering techniques results in enhanced drain current and reduced SCE’s of low leakage current, threshold voltage roll-off and drain induced barrier lowering.

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An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays: Digital and Analog Figures of Merit from 300K to 10K

Cited by 12 publications

References 6 publications

WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake

Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current

3D Analytical Modeling Of Surface Potential And Threshold Voltage Model Of Dm Fintfet With Dual Hetero Gate Oxide Structure

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