2020
DOI: 10.1016/j.jallcom.2020.155908
|View full text |Cite
|
Sign up to set email alerts
|

Low-temperature formation of platinum silicides on polycrystalline silicon

Help me understand this report
View preprint versions

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2022
2022
2024
2024

Publication Types

Select...
6

Relationship

0
6

Authors

Journals

citations
Cited by 7 publications
(1 citation statement)
references
References 23 publications
0
1
0
Order By: Relevance
“…For example, ohmic contact with the lightly doped thin device layer is best achieved by the formation of a thin layer of PtSi alloys at the interface of Ta/Pt and silicon. However, this process is too sensitive to the thickness of the silicide formation and the annealing temperature to provide reproducible results with our device layer thickness [ 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 ]. We have overcome this issue by optimization of the annealing process to get a reliable planar junctionless FET device, and in the end, we have demonstrated the pH sensing performance of our fabricated device.…”
Section: Introductionmentioning
confidence: 99%
“…For example, ohmic contact with the lightly doped thin device layer is best achieved by the formation of a thin layer of PtSi alloys at the interface of Ta/Pt and silicon. However, this process is too sensitive to the thickness of the silicide formation and the annealing temperature to provide reproducible results with our device layer thickness [ 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 ]. We have overcome this issue by optimization of the annealing process to get a reliable planar junctionless FET device, and in the end, we have demonstrated the pH sensing performance of our fabricated device.…”
Section: Introductionmentioning
confidence: 99%