Low-Temperature Microwave Annealing for MOSFETs With High-k/Metal Gate Stacks

Lee, Yao-Jen; Tsai, Bo-An; Lai, Chao-Hung; Chen, Zheng-Yao; Hsueh, Fu-Kuo; Sung, Po-Jung; Current, Michael; Luo, Chih-Wei

doi:10.1109/led.2013.2279396

Cited by 16 publications

(2 citation statements)

References 8 publications

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“…On the other hand, the fabrication process of Ge MOSFETs should be kept at low temperature to suppress dopant diffusion and avoid the generation of interfacial defects. Thus, microwave annealing (MWA) with low thermal budget was used to activate the dopant in the source and drain (S/D) regions [17]. Low-temperature MWA utilizes microwave radiation with longer wavelengths to penetrate atoms directly, thereby inducing lattice vibrations and facilitating uniform heating throughout the material.…”

Section: Introductionmentioning

confidence: 99%

3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET

Lin,

Chen

et al. 2023

IEEE J. Electron Devices Soc.

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In this study, we propose a self-aligned stacked Ge nanowire (NW) p-type gate-all-around field-effect transistor (pGAAFET) on Si nFinFET of single gate complementary FET (CFET). The self-aligned stacked Ge NW pGAAFET on Si nFinFET of single gate CFET device is fabricated on a SOI wafer. The CFET device is fully compatible with current Si technology platform using alternating anisotropic and isotropic dry etching process. The Ge NW pGAAFET presents an on-state current (ION) of 166 A/m at VD = VG-VTH = -0.5 V and shows minimum subthreshold swing (SSmin) of 79, 91 mV/dec, and ION/IOFF of 3.03 × 10 5 , 3.4 × 10 4 at VD = -0.05 V and -0.5 V, respectively. The Si nFinFET presents an ION of 60.4 A/m at VD = VG-VTH = 0.5 V and shows SSmin of 91, 101 mV/dec, and ION/IOFF of 9.01 × 10 4 , 5.62 × 10 5 at VD = 0.05 V and 0.5 V, respectively. The proposed CFET can simplify the process and shows promising potential for extending scaling beyond the technology node.

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Section: Introductionmentioning

confidence: 99%

3-D Self-Aligned Stacked Ge Nanowire pGAAFET on Si nFinFET of Single Gate CFET

Lin,

Chen

et al. 2023

IEEE J. Electron Devices Soc.

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“…Microwave annealing increases the molecular rotational and polarization energies of dopants for activation [6], [7]. Microwave annealing is performed at low temperature, which suppresses the diffusion of dopants.…”

Section: Introductionmentioning

confidence: 99%

Low-Temperature Microwave Annealing for Tunnel Field-Effect Transistor

Jhan

Wang

et al. 2015

IEEE Electron Device Lett.

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Unlike the high-temperature activation of dopants, such as rapid thermal annealing (RTA), the activation of dopants by low-temperature microwave annealing (MWA) suppresses their diffusion, reducing screening tunneling length (λ). This letter compares low-temperature (490°C) MWA with high-temperature (1050°C) RTA of a fin-shaped polycrystalline silicon (Poly-Si) tunnel field-effect transistor (TFET). The band-to-band tunneling voltage (V BTBT ) indicates clearly that TFET annealed by MWA had a lower λ than TFET that was annealed by RTA. The TFET that was annealed by MWA had a high ON/OFF current ratio of 10 8 , a low subthreshold swing, and an almost negligible drain-induced barrier lowering.Index Terms-Tunnel field-effect transistor (TFET), microwave annealing (MWA), screening tunneling length (λ), band-to-band tunneling (BTBT).

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