І. INTRODUCTION According to the ITRS, the thickness of gate oxide in 2007 will be reduced to 1.1nm. However, the nm-scale SiO 2 thin film increases leakage current drastically and cannot be used because of large power dissipation. In recent years, high-k dielectric has obtained much attention to replace SiO 2 gate insulator for the applications of ULSI [1][2]. Then, high gate capacitance or low equivalent oxide thickness thus can be achieved simultaneously with low gate currents. One of the most promising deposition techniques for high-K materials is atomic layer deposition (ALD) , since it is manufacturabe and provides excellent conformality and uniformity [3][4]. In ALD, materials are deposited layer by layer in a selflimiting fashion, allowing for inherent atomic scale control. The most widely used ALD precursors for metal oxides are metal-chlorides, such as HfCl 4 and Al(CH 3) 3. Unfortunately, metal oxide formed by a ALD using metal chloride precursors exhibits poor initial deposition on H-terminated Si[5][6], necessitating the use of an interfacial SiO 2 or Si 3 N 4 layer to achieve uniform growth. However, the interfacial layer between the high-K layer and silicon substrate can have an opposing effect on this pursuit of low effective oxide thickness (E OT) and low gate currents. Since an E OT of less than 1 nm will soon be required, the need for an initial few monolayers of a lower dielectric constant material would be a serious drawback. Interfacial SiO 2 layers are conventionally produced by the thermal oxidation at temperatures above 800 °C in O 2 or N 2 O. The high performance of MOS devices relies on almost perfect characteristics of the Si/SiO2 interfaces. However, the serious problem is that the control of the SiO 2 thickness becomes very difficult because of the high Si oxidation rate at high temperatures. In the present study, we will discuss the chemical oxide formed in HNO 3 , SCl, and H 2 SO 4. A high temperature spike annealing treatment is performed to decrease the chemical oxide thickness and then use it as the interfacial layer of high K dielectric. Characteristics of the gate stack of TaN/HfAlO/chemical oxide/Si are also compared and discussed, simultaneously. П. Device Fabrication The starting material was wafer of 6-in Si (100) with 15~25 Ω-cm, and it was clean using RCA methods. The first group samples are MOS devices with TaN/ SiO 2 /Si structures. Gate dielectric was performed by immersing wafers in to chemical solutions (HNO 3 , NH 4 OH+H 2 O 2 (SC1), and H 2 SO 4). After the formation of chemical oxide layers, TaN layer was carried out in PVD system for gate electrode, and then annealed by RTA at 850 °C for 30-sec.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.