Low Tinv (≤ 1.8 nm) Metal-Gated MOSFETs on SiO2 Based Gate Dielectrics for High Performance Logic Applications

Abstract

We present results on mid-gap metal gated MOSFETs using CoSi 2 & W with Si oxide & oxynitride gate dielectrics. For CoSi 2 gates, we demonstrate a simple integration scheme using silicidation of the polysilicon (poly) gate with low nFET Tinv~1.7nm. For the W gate stack, we use a replacement gate process resulting in a pFET Tinv~1.8 nm. W pFET mobility is comparable to poly, while nFET peak mobility is degraded.

Advanced high-κ dielectric stacks with polySi and metal gates: Recent progress and current challenges

“…After deposition, the highest temperatures to which the gate stacks are exposed are those observed in the back end, which are typically ,5008C. Using the replacement-gate integration scheme and CVD W as a metal gate, CMOS transistors down to 0.1 lm were successfully fabricated [88]. It was shown that while the hole mobility of p-FETs remains as good and in some cases better than that of polySi/SiON controls, the electron mobility for W/SiO 2 , W/SiON [88], and W/HfO 2 /SiON [ Figure 7(a)] were degraded by more than 20% compared with polySi/SiON gate stacks of similar T inv .…”

“…Using the replacement-gate integration scheme and CVD W as a metal gate, CMOS transistors down to 0.1 lm were successfully fabricated [88]. It was shown that while the hole mobility of p-FETs remains as good and in some cases better than that of polySi/SiON controls, the electron mobility for W/SiO 2 , W/SiON [88], and W/HfO 2 /SiON [ Figure 7(a)] were degraded by more than 20% compared with polySi/SiON gate stacks of similar T inv . It was also clear that the presence of N in the gate stack further degrades the electron mobility for a lowtemperature integration process [88].…”

“…It was shown that while the hole mobility of p-FETs remains as good and in some cases better than that of polySi/SiON controls, the electron mobility for W/SiO 2 , W/SiON [88], and W/HfO 2 /SiON [ Figure 7(a)] were degraded by more than 20% compared with polySi/SiON gate stacks of similar T inv . It was also clear that the presence of N in the gate stack further degrades the electron mobility for a lowtemperature integration process [88]. Figure 7(b) is a representative TEM image of the center of a 1-lm trench for a W/HfO 2 /SiON stack.…”