Low-variation SRAM bitcells in 22nm FDSOI technology

Joshi, Vivek; Ramamurthy, Hema; Balasubramanian, Sriram; Seo, Soon‐Cheon; Yoon, Hongil; Zou, Xuecui; Chan, N.; Yun, Jang−Gn; Klick, T.; Smith, E.E.; Schmid, J.; vanBentum, R.; Faul, J.; Weintraub, C.

doi:10.23919/vlsit.2017.7998179

Cited by 13 publications

(5 citation statements)

References 2 publications

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“…In order to enable isolated word reading/programming and to avoid sneaky current paths, an N-type MOSFET is located at the wordline output as a selector device. Despite the larger Z 2 -FET cell size ( 0.2 µm 2 ) with respect to a 6T-SRAM in 28FDSOI technology [8] ( 0.125 µm 2 ), TCAD simulations prove the cell is functional for reduced dimensions [9], drastically reducing its footprint.…”

Section: Introductionmentioning

confidence: 99%

Experimental Demonstration of Operational Z²-FET Memory Matrix

Vilanova

Navarro

Márquez

et al. 2018

IEEE Electron Device Lett.

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In this work, a functional Z 2 -FET DRAM memory matrix is experimentally demonstrated for the first time. Wordlevel operation with simultaneous reading and programming accesses is successfully proved. Disturbance is also explored, and the results demonstrate bitline disturbance immunity. Furthermore, the fabricated memory matrix, which includes only one selector per word-line, facilitates the scalability of the memory for increasing array dimensions.

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Section: Introductionmentioning

confidence: 99%

Experimental Demonstration of Operational Z²-FET Memory Matrix

Vilanova

Navarro

Márquez

et al. 2018

IEEE Electron Device Lett.

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“…This technology has the advantages of both planar and finFET technologies. It promises almost finFET-like performance in a planar technology, without the increased variation and which greatly benefits layout constraints [9]. Thus, it fits all requirements for a mixed-signal biomedical system.…”

Section: A 1mhz 256kb Ultra Low Power Memory Macromentioning

confidence: 98%

“…Aggressive stand-by voltage scaling with foundry macros is possible, but limited to around 400mV in 28-22 nm technologies due to local process variation [3], [16], even with the low variation promised in the 22nm FD-SOI technology [9]. In this voltage range, the macros are in near-threshold operation.…”

Section: A Lower Retention Voltagementioning

confidence: 99%

A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage

Vanhoof,

Dehaene

2024

IEEE Trans. Circuits Syst. I

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In biomedical sensor platforms, low energy consumption is of utmost importance to extend battery life. A dominant contributor in the energy budget of such platforms is the always-on recording memory. Hence, a low energy memory is required. This paper implements such a memory with aggressive voltage scaling to run the memory in the sub-threshold region during retention. Fine grained forward error correction is a key enabler for this. It allows operation of the memory beyond the point of first failure and acts similar to EDAC techniques for timing failure detection in voltage-scaled microcontrollers. The memory is embedded in a RISC-V microcontroller and fabricated in a 22nm FDSOI technology. Measurements show an always-on retention voltage down to 170mV, which results in a total average power of only 5.11uW, a 70% reduction compared to the signoff point. The memory is extensively tested with memtest and found to be fully functional up to 1.2 MHz.

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“…As shown, d SOI is explicitly given in the article that reports σ examined here [19]. We estimated A and V DR from an article [28] that reports a similar 22-nm SOI SRAM, which was fabricated by the same manufacturer as the part being examined. Specifically, A and V DR were, respectively, estimated by analyzing a scanning electron microscope (SEM) image and butterfly curves under various V DD conditions.…”

Section: B 22-nm Soi Srammentioning

confidence: 99%

An SRAM SEU Cross Section Curve Physics Model

Kobayashi

Hirose

Sakamoto

et al. 2022

IEEE Trans. Nucl. Sci.

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Static random access memories (SRAMs) are prone to a single-event upset (SEU), also known as soft errors, due to transient noise caused by a single strike of radiation. Beam testing has been extensively used to measure the SEU cross section of SRAMs as a function of the linear energy transfer (LET) of charged particle radiation. The evolution of the cross section as a function of LET is called the cross section curve, which plays a vital role in upset rate analysis for hardness assurance. Various analytical models have been developed to describe SRAM SEU cross section curves, and they have proven to be useful in reducing the cost of beam testing as well as revealing the physics behind test results. However, they involve arbitrary parameters, which make it challenging to predict cross section curves without any beam results. Moreover, the current method of analyzing cross section curves or the LET dependence of cross sections relies on a model different from that is used in the analysis of power-supplyvoltage dependence, which is becoming increasingly important because of the demand for low-power operation. To overcome these problems, this article proposes a unified equation that describes both LET and the power-supply-voltage dependence of SRAM SEU cross sections. It comprises only parameters that are physically clear and familiar to SEU researchers. As well as giving possible constraints, comparisons with data from the literature suggest it can be applied to SRAMs fabricated in bulk and silicon-on-insulator (SOI) processes across generations from the early 1000-nm-scale to the current 10-nm-scale technology nodes.

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Low-variation SRAM bitcells in 22nm FDSOI technology

Cited by 13 publications

References 2 publications

Experimental Demonstration of Operational Z²-FET Memory Matrix

Experimental Demonstration of Operational Z²-FET Memory Matrix

A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage

An SRAM SEU Cross Section Curve Physics Model

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Low-variation SRAM bitcells in 22nm FDSOI technology

Cited by 13 publications

References 2 publications

Experimental Demonstration of Operational Z2-FET Memory Matrix

Experimental Demonstration of Operational Z2-FET Memory Matrix

A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage

An SRAM SEU Cross Section Curve Physics Model

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Experimental Demonstration of Operational Z²-FET Memory Matrix

Experimental Demonstration of Operational Z²-FET Memory Matrix