Low voltage dual mode logic: Model analysis and parameter extraction

Levi, Itamar; Kaizerman, Asaf; Fish, Alexander

doi:10.1016/j.mejo.2013.03.005

Cited by 37 publications

(15 citation statements)

References 16 publications

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“…These gates are used as building blocks for the development of the Sub-Clock CMOS circuits in order to reduce the power consumption and also the leakage current. The power consumed by the sub-clock circuit is only about 46% when compared to the ideal circuit [1]- [7]. Similarly the energy consumed by the circuit is also reduced up to 40% compared to the existing/ideal circuits.…”

Section: Resultsmentioning

confidence: 98%

“…Here the full adder is designed with the two EX-OR gates and three AND gate and also with two numbers of the OR gate which is designed in BTC technique. The full adder designed in the papers [7]- [13] are depend only on the sizing of the transistor, reducing the finger width of the transistor due to this the circuit consume less power, even the power reduction is done due to the low width the circuit is not used in the complex design. To avoid these drawbacks the BTC is used in the two type of methodology as shown Figure 7 and Figure 8.…”

Section: Full Adder Design Using Btcmentioning

confidence: 99%

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Design and Analysing the Various Parameters of CMOS Circuit’s under Bi-Triggering Method Using Cadence Tools

Sridevi¹,

LakshmiPrabha²,

Prabhu³

2016

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Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The proposed triggering method uses a complementary MOS transistor (pMOS and nMOS) as a voltage divider and ground leakage suppressor (i.e.); these designs are named as Trig01 and Trig10 designs. In Trig01 design the pair of CMOS is placed in the voltage divider part; similarly in Trig10 design the pair of CMOS is placed at the ground leakage suppressor part. Standard CMOS gates like NOT, NAND, NOR, EX-OR etc. are designed with these technologies and these gates are designed with 180 nm technology file in the cadence tool suite; compared to the normal CMOS gates, the Bi-Trig gate contains 4 inputs and 2 outputs. The two extra inputs are used as Bi-Trig control signaling inputs. There are 2 control inputs and thus 2 2 = 4 combination of controlling is done (i.e.); both pMOS and nMOS are ON, both pMOS and nMOS are OFF, pMOS ON and nMOS OFF and pMOS ON and nMOS ON. Depending on the usage of the circuit, the mode of operation is switched to any one of the combination. If the output of the circuit is not used anywhere in the total block, that specified circuit can be switched into idle mode by means of switched OFF both the pMOS and nMOS transistor in the control unit. This reduces the leakage current and also the power wastage of the circuits in the total block. Bi-Trig controlled circuit reduces the power consumption and leakage power of the circuit without affecting a performance of the circuits. KeywordsBi-Triggering, Power Analysis, Energy Analysis, Circuit Simulation, Delay Analysis, Sub Clock Method A. Sridev et al. 2623

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Section: Resultsmentioning

confidence: 98%

Section: Full Adder Design Using Btcmentioning

confidence: 99%

Design and Analysing the Various Parameters of CMOS Circuit’s under Bi-Triggering Method Using Cadence Tools

Sridevi¹,

LakshmiPrabha²,

Prabhu³

2016

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“…DML gate can be used for switching between static and dynamic mode of circuit operation as per the requirement. Energy efficiency with moderate performance can be achieved in static mode, whereas performance efficiency can be achieved by losing energy efficiency in dynamic mode [13]. Differential Cascode Voltage Switch Logic (DCVSL) and Complementary Pass Transistor Logic (CPTL) are other circuit designing techniques with some different circuit structure and higher delay.…”

Section: Previous Contributionmentioning

confidence: 99%

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

Sharma*,

Sohal

2019

IJITEE

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In this paper we propose a power efficient technique called Sleepy- Gate Diffusion Input (S-GDI) that can be used for efficient digital design at nano scale foundries. For area and power comparison, ten prior techniques are taken in to consideration and applied on XOR gate, 1-bit adder, 1-bit comparator and 4- bit up-down counter. All techniques are parametrically analyzed on 65nm technology. The proposed S-GDI technique has been observed power efficient as compared to Complementary CMOS technique (CCT), Complementary Pass Transistor Logic (CPTL), DCMOS (Differential CMOS), Differential Cascode Voltage Switch with Pass Gate Logic (DCVSPG), Energy Economized Pass Transistor Logic (EEPL), Lean Integration with Pass Transistors (LEAP), Push-Pull Pass Transistor Logic (PPL), Pass Transistor Logic (PTL), CMOS with Transmission Gate (TG) and Gate diffusion Input (GDI). As compared to GDI technique S-GDI is showing 96.20%, 93.65%, 97.88% and 98.22% power efficiency for XOR, 1-bit adder, 1-bit comparator and 4-bit up-down counter respectively. S-GDI is showing area efficiency of 17.16% and 28.1% for XOR, 41.26% and 53.89% for 1-bit adder, 7.6% and 21.76% for 1-bit comparator and 6.7% and 28% for up-down counter over EEPL and DCMOS technique respectively. Although other techniques except EEPL and DCMOS techniques are area efficient as compared to proposed technique but this is on the expense of higher total power dissipation. So, PDP (power delay products) of all considered techniques are also calculated on 65nm technology for both SUM and CARRY outputs of 1-bit adder. In both cases power delay product for S-GDI technique is very less as compared to all other considered technique. Due to efficiency of S-GDI in terms of considered parameters, this technique can be efficiently used for low power applications

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“…5. In DML the M1 transistor and all transistors in pullup or pull-down network which compose a parallel path with M1 are designed to have the minimum size while other transistors in complementary network are sized according to standard CMOS logic [11]. In static mode, M1 goes off (clk¼V DD ) and DML structure is similar to a standard-static CMOS logic with an extra parasitic capacitance (M1) but using above mentioned sizing method causes less power consumption.…”

Section: Dual Mode Tgdi Logicmentioning

confidence: 99%

“…Also in dynamic mode, an asymmetric clock is applied to M1 and creates pre-charge and evaluation phases. Pre-charging is performed by a minimum sized M1 transistor and its parallel network acts as an active keeper, which provides more robustness in comparison with domino logic [11], and also solves some drawbacks of domino logic such as crosstalk noise, charge sharing and sensitivity to glitches [7]. By replacing CMOS circuit with TGDI in DML structure DMTGDI logic is obtained according to Fig.…”

Section: Dual Mode Tgdi Logicmentioning

confidence: 99%