Low-Voltage Embedded-RAM Technology: Present and Future

Abstract

Abstract:First, key issues for low-voltage «IV) embedded RAMs are summarized in terms of stable operation, suppression of leakage (gate-tunneling/subthreshold) currents, and speed variation of memory cells and peripheral logic circuits. Next, DRAM and SRAM cells to cope with the above issues, the circuit design focusing on subthreshold-current issue, and suppression of or compensation for design-parameter variations to reduce the speed variations are discussed. Voltage converters and power management for low-power and low-voltage operation are also explained. Finally, based on the above discussions, a perspective is given with emphasis on needs for simple/high signal-to-noise ratio memory cells (such as gain cells) with a pure logic compatible process, high-speed subthreshold-current reduction focusing on active mode, and memory-rich SoC architectures.

Trends in low-voltage embedded-RAM technology

“…1) [2]. Here, the dual-V DD and dual-tox device approach has been maintained with a MOSFET that has a thicker-tox and higher V T for the higher-V DD I/O circuitry.…”

“…The substrate forward biasing recently proposed [6] achieves a larger V Tchange for a given V SUB -swing, even though the forward bias is strictly limited to less than 0.4V due to a rapid increase in the substrate current. The required V SUB swing, however, is as large as 1-3 V (Fig.5(b)) [2] and this approach becomes less effective with device scaling [7]. This is beacause of the smaller body constant, enhanced short-channel effects, and increases in other leakage currents such as the gate-induced drain-lowering (GIDL) current [7].…”

“…A good example is the so-called 1-T SRAM TM [11], in which a 1-T DRAM cell with a C S as small as less than 10 fF is realized by a single poly-Si planar capacitor, and an extensive multi-bank scheme with 128 banks (32 Kb in each) that are simultaneously operable is used. Lowvoltage high-speed sensing is also essential [2] for the wellknown mid-point sensing by which the data-line power is halved without using a dummy cell, since using the half-V DD data-line voltage makes the sense-amplifier operation quite slow. Thus, many attempts [2] have been made.…”

“…Lowvoltage high-speed sensing is also essential [2] for the wellknown mid-point sensing by which the data-line power is halved without using a dummy cell, since using the half-V DD data-line voltage makes the sense-amplifier operation quite slow. Thus, many attempts [2] have been made. SRAM: Of the many proposed designs [1], the 6-T full-CMOS cell (Fig.8) is most suitable despite the fact that it is large.…”

“…For RAM cells, in addition to leakage current suppressions, stable operation to cope with reduction of signal charge due to low V DD is vital. Other design issues for low-V DD operation [2], such as on-chip supply-voltage converters, power management, testing methodology, and DA tools to manage the subthreshold current are also crucial.…”