Low-voltage hot-electron currents and degradation in deep-submicrometer MOSFETs

Abstract

= 7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bia5 as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed as drain biases as low as 1.8 V. These voltages are believed to be the lowest repnrted values for which hotelectron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hotelectron effects present at higher biases and longer channel lengths. N o critical voltage for hot-electron effects (such as the Si-Si02 barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 am) and oxide thicknesses.

Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

“…Equation (13) is fitted with the experimental versus data and the parameters and are obtained. By obtaining from (10) and from (12), the interface-trap profile is constructed using (8) and (11). The profile is then constructed using either (5) or (6).…”

“…It has been found that the reduction of MOSFET channel length increases the carrier heating process [9], [10]. Moreover, due to nonscaling of the region of the channel damaged by hot carriers, a relatively larger fraction of the channel gets affected for smaller channel lengths [11], [12]. Both these effects have a stronger impact on device characteristics and hence the degradation has been found to worsen with reduction in channel length [3], [4], [9]- [12].…”

Impact of Gate Oxide Thickness Scaling on Hot-Carrier Degradation in Deep-sub-micron nMOSFETs

“…In the light of the non-linear behavior of V¢ at low V£ seen in figure 2, it is important to verify whether hot-carrier life time prediction algorithms based on the lucky electron model [1] are still valid at such drain voltages. Figure 3 compares the measured data with the lucky electron model for the I §¨ condition and a fixed V¢ condition for V£ down to 0.9V for a T¤ ¥ of 3nm.…”

“…Impact ionization is reported in silicon nMOSFETs for drain voltages (V£ ) down to 0.7V [1], well below the bandgap voltage for silicon. Recently it was also suggested that the hot-carriers need not necessarily get injected into the gate dielectric to cause in-terfacial degradation [2].…”

“…It was reported that the hotcarrier reliability improves with oxide thickness (T¤ ¥ ) scaling [3] and that the lucky electron model can be used to predict the hot-carrier life time for very low V£ [1,4]. But there is no consistency in the literature on the bias conditions used for stress, with some workers using V¢ =V£ /2 [4,6,7] and some others using peak I §¨ [5] as the worst case degradation condition.…”