Low‐voltage low‐power CMOS receiver front‐end for gigabit short‐reach optical communications

An adaptive continuous-time equalizer for reliable short-haul high-speed serial communications is described in this paper. The adaptive equalizer uses the spectrum-balancing technique to adapt its response to changes in the bandwidth, amplitude, and bit rate of the input signal. In this way, it is able to compensate the frequency response of a 1-mm diameter step-index plastic optical fiber, for lengths up to 50 m, and bit rates ranging from 400 Mb/s to 2.5 Gb/s. Experimental results are shown to demonstrate its feasibility. Copyright transmission channel to meet the high data rate requirement. Therefore, the faster the communication required, the higher signal equalization is needed [5].In a previous work [6], an analog line equalizer cell aimed to compensate the limited frequency response of SI-POF was proposed. In a real communications link, however, there are many other factors that degrade the transmitted signal, such as the losses inherent to the physical material of the fiber (0.14 dB/m at 650 nm), the capacitance of the receiver PD (whose diameter is larger than 0.4 mm), and the bandwidth-length trade-off (~50 MHz · 100 m). Considering the previously mentioned variations expected, the line equalizer needs a mechanism to automatically adapt its frequency response accordingly and avoid to over-compensate or under-compensate the signal, which otherwise would increase the bit error rate.Hence, the equalizer proposed here is implemented altogether with two feedback loops to independently adjust both the boosting and the gain to compensate variations in bandwidth and amplitude of the received signal.In addition, by means of the wavelength-division multiplexing technique, a single optical link is able to transmit a number of optical carrier signals by using different wavelengths. In consequence, it is possible to transport different standards, such as Synchronous Optical Networkin OC-9 (466 Mb/s) and Synchronous Digital Hierarchy STM-16 (2.5 Gb/s), and it is expected to allow different data rates in the same receiver. Therefore, a multi-rate characteristic is a must if the equalizer is to be fully implemented in such applications.Several techniques can be used to implement the equalizer circuit and to choose the right equalization strategy depending on the particular application and channel characteristics. In the case of POF links, several authors use decision feedback equalization (DFE) (always with a previous linear equalizer) with some algorithms such as least mean square or minimum mean square to implement the adaptation [7]. Although DFE is an effective strategy for channels with severe intersymbol interference, for short lengths (up to 100 m), the advantage in performance between a DFE and a linear one is much less, and it may not justify the increase of complexity, area, and power consumption [8]. Therefore, an analog continuous-time equalizer is preferred in this case as they present a good trade-off for low-power, high-speed applications, reducing design complexity and area.Although some receivers with ...

Section: Gain Adaptation Loopmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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Design of a CMOS multi‐rate adaptive continuous‐time equalizer based on power spectrum estimation

Gimeno

Guerrero

Sánchez-Azqueta

et al. 2017

“…Various noise sources behave quite differently. Accordingly, different noise sources must apply individual detection techniques [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. In this paper, we focus on PSN detection.…”

Section: Introductionmentioning

confidence: 99%

Wide bandwidth and high precision power supply noise detector by using dual peak detection sample and hold circuits

Wey¹,

Peng²,

Chow³

2012

SUMMARY In this paper, we proposed a high‐performance, high‐precision power supply noise (PSN) detector by using dual peak detection sample and hold circuits with source follower. By using dual peak detection sample and hold circuits, we can avoid PSN missing detection and therefore avoid massive PSN detection error. We also added one dummy switch to cancel the charge injection effect and to improve the PSN detection accuracy. In the proposed design, we applied one PMOS type charging circuit to enhance the operation frequency of differential amplifier, which can widen both the PSN detection bandwidth and the detection range. As a result, in the proposed PSN detection circuit, the PSN detection bandwidth can be raised from 1 GHz to 2 GHz with the PSN detection error lowered to ±3%. Moreover, the PSN detection range is widened from 10%–50%VDD to 5%–65%VDD as compared with the state‐of‐the‐art design. Copyright © 2012 John Wiley & Sons, Ltd.

A 1–6 GHz analog radio frequency power driver in 90 nm complementary metal‐oxide semiconductor technology for wireless applications

Ren

Abraham

Hong

2013

SUMMARYOne of the most challenging subsystems for integrated radio frequency (RF) complementary metal-oxide semiconductor (CMOS) solutions is the power amplifier. A 1-6 GHz RF power driver (RFPD) in 90 nm CMOS technology is presented, which receives signals from on-chip RF signal chain components at À12 dBm power levels and produces a 0 dBm signal to on-chip or off-chip 50 Ω loads. A unique unit cell design is developed for the RFPD to offset issues associated with very wide multi-fingered transistors. The RF driver was fabricated as a stand-alone sub-circuit on a 90 nm CMOS die with other sub-circuits. Experimental tests confirmed that the on-chip RFPD operates up to 6 GHz and is able to drive 50 Ω loads to the desired 0 dBm power level. Spur free dynamic range exceeded 70 dB. The measured power gain was 11.6 dB at 3 GHz. The measured 1 dB compression point and input third-order intercept point (IIP3) were À4.7 dBm and À0.5 dBm, respectively. Also, included are modeling, simulation, and measured results addressing issues associated with interfacing the die to a package with pinouts and the package to a printed circuit test fixture. The simulations were made through direct current (DC), alternating current (AC), and transient analysis with Cadence Analog Design Environment. The stability was also verified on the basis of phase margin simulations from extracted circuit net-lists.