Low-voltage low-power LVDS drivers

Chen, Mingdeng; Silva-Martí­nez, J.; Nix, M.; Robinson, M.E.

doi:10.1109/jssc.2004.840955

Cited by 107 publications

(11 citation statements)

References 4 publications

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“…While power consumption under different loads without self-adaptive technology are represented by three curves marked as 'Without self-adaptive@1 pF load', 'Without self-adaptive@5 pF load' and 'Without self-adaptive@10 pF load'. Power consumption results of reference [3], reference [4] and reference [14] are represented by data points marked as 'Ref. [14]@5 pF'.…”

Section: Resultsmentioning

confidence: 99%

“…But in DCS, only the current of one branch can be delivered to the load, therefore half of the power consumption is wasted. Switchable current source (SCS) [3] architecture eliminates power wasting in DCS by only turning on the current source which provides load current through S1 and S2 in Fig. 1(b), but switch S1 and S2 will introduce extra jitter in SCS.…”

Section: Introductionmentioning

confidence: 99%

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Design of a power efficient self-adaptive LVDS driver

Wang

Lai

2018

IEICE Electron. Express

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A self-adaptive technique is presented for a low voltage differential signaling (LVDS) driver. By combining a high speed voltage detection circuit and drive capability control loop, the proposed architecture can adapt to the changes of output load and operating frequency automatically. This makes the driver suitable for using in field programmable gate array (FPGA), where load and frequency variation is large. Compared to previously reported LVDS drivers with fixed drive capability, the proposed driver eliminates power wasting under small load and low frequency condition. A prototype chip has been fabricated in 130 nm CMOS technology. Test results show the proposed driver improves maximum bit rate to 2.2 Gb/s and reduces power consumption by 48% compared to previously reported works with fixed drive capability.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design of a power efficient self-adaptive LVDS driver

Wang

Lai

2018

IEICE Electron. Express

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“…A predictable SNDR degradation can be noted at high input frequencies due to sampling phase mismatch. However, after the manual delay cells adjustment on each sampling phase, 6 The total random RMS jitter in the clock sampling phases is estimated from measurements in 1.9 ps. This jitter value is low enough to achieve the ideal 6 ENOB at 1 GHz sinusoidal input signal.…”

Section: Lvds Pre-emphasis Resultsmentioning

confidence: 99%

“…However, the requirements of the emulation platform about variable F s and wide time delay control have limited the jitter performance optimization. The clock jitter could be drastically reduced if the delay- 6 Each delay cell was adjusted by an iterative method to find the best SNDR of a sinusoidal input signal at near Nyquist frequency. 6 mW), and the delay cell (3.2 mW).…”

Section: Lvds Pre-emphasis Resultsmentioning

confidence: 99%

“…An LVDS driver is basically a current mode differential driver that can be implemented in several topologies. The driver topology used in this implementation is the bridgedswitches current source (BSCS) [3,6]. This topology is simple, features a low power consumption and can operate at the 2.5 V supply voltage that is available for the I/O ports of the chip.…”

Section: Drivermentioning

confidence: 99%

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A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

Reyes

Paulina²,

Sánchez³

et al. 2015

Analog Integr Circ Sig Process

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A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 lm CMOS process. The architecture uses 8 time-interleaved track-andhold amplifiers (THA) and 16 asynchronous SAR ADCs. The sampling frequency of the TI-ADC can be set from 200 MHz to more than 2 GHz. The chip includes a programmable delay cell array to adjust up to AE25 % the sampling clock phase in each THA, and a multi-channel low voltage differential signaling interface capable of transmitting at full sampling rate (>12 Gb/s), without decimation, off-chip. These blocks make the fabricated ADC an excellent platform to test/evaluate mixed-signal calibration algorithms, which are of great interest for application in high-speed optical systems. Measurements of the fabricated ADC show a peak signal-to-noise-and-distortion ratio of 33.9 dB and a power consumption of 192 mW at 1.2 V.

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A configurable 2‐Gbps LVDS transceiver in 150‐nm CMOS with pre‐emphasis, equalization, and slew rate control

Jawed

Ali

Khan

et al. 2016

Circuit Theory & Apps

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Summary A configurable full‐duplex low‐voltage differential signaling transceiver is presented, which can be configured to operate either for smaller differential channels (a few inches of striplines) or for longer channels (10 m of twisted pair cables). The configurability is embedded in the form of functionalities like pre‐emphasis, equalization, and slew rate control within the transceiver. The transmitter employs a hybrid voltage–current‐mode driver, which due to replica action, achieves a high‐impedance current‐mode signal dispatch and at the same time provides a matched impedance at the near end for improved intersymbol interference. The transmitter achieves slew rate control through a band‐limited pre‐driver, while the pre‐emphasis is achieved through a capacitive feed‐forward. The receiver employs a large‐input common‐mode first stage enclosed in a common‐mode control loop that enables its first stage to also act like a domain shifter (VDDIO‐to‐VDDCORE) reducing the overall power consumption. The equalization in the receiver is implemented by using carefully sized active inductive loads inside the receiver. The transceiver is designed and fabricated in 150‐nm complementary metal–oxide–semiconductor, sharing the space with a larger die, occupying an area of 400 × 400μm. The measurement results demonstrate that the transceiver is operating at 2 Gbps both for a 4‐in microstrip and a 10‐m twisted pair CAT6 cable with 30 and 180 ps of total jitter, respectively. The built‐in impedance calibrator minimizes the spread in the on‐die termination at the near end provided by the transmitter‐minimizing bit error rate across process, voltage, and temperature corners. The transmitter consumes a total power of 17 mW operating at 2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps. Copyright © 2016 John Wiley & Sons, Ltd.

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Low-voltage low-power LVDS drivers

Cited by 107 publications

References 4 publications

Design of a power efficient self-adaptive LVDS driver

Design of a power efficient self-adaptive LVDS driver

A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques

A configurable 2‐Gbps LVDS transceiver in 150‐nm CMOS with pre‐emphasis, equalization, and slew rate control

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