This paper presents four topologies of voltage-mode un-terminated IO cells in 28-nm CMOS for singleended rail-to-rail signaling over a passive interposer die in 2.5D configuration for >1Gbps data rates. The presented design explores the existing IO design-space from a 2.5D viewpoint, optimizing existing topologies from area, speed, power and protection perspectives, with a higher degree of configurability in the form of pre-emphasis and slew-rate control. The transmitter (TX) embeds pre-emphasis to enhance high-frequency components of the signal for longer low-pass natured channels. The TX also implements slew-rate control to minimize reflections on shorter channels because of impedance discontinuities and also to minimize simultaneous switching noise. Level-shifting capability embedded in the receiver (RX) enables multi-technology interfacing where different dies are signaling at their core voltages (range: 0.7 V-1.8 V) instead of following a particular signaling standard. The measurement results of the transceivers, over a interposer of length of 3.5 mm, demonstrate ±5% duty-cycle distortion with 700 μW at 500 MHz/0.8-V-signaling on the channel with jitter of 20 ps, ±10% duty-cycle distortion with 1.8 mW at 1Gbps/0.9-V signaling with jitter of 20 ps, ±10% duty-cycle distortion with 2 mW at 2Gbps/0.7-V signaling for 1-V receiver core voltage with a jitter of 10 ps. of limiter material or functional errors because of electro-thermal coupling or excessive leakage currents which can form a positive feedback loop with the temperature leading to thermal run-away problem [10,11]. Moreover, the thermal expansion coefficients of TSV material and substrate are different, which can result in large temperature induced mechanical stress again leading to nonuniform distribution of delay across the area [5].Recently, 2.5D IC stacking has emerged as a viable alternative because of its higher mechanical and thermal reliability with a comparable interconnect density [10,12,13]. Several flip-chip dies are attached with fine-pitch micro-bumps to a single passive interposer die also known as throughsilicon-interposer (TSI) communication. This interposer die allows connections between adjacently placed multi-technology dies as well as connections to the package, providing low interconnect delay, high-bandwidth, multi-technology interfacing and reduced ESD protection requirements for die-to-die connections [14]. Moreover, although incurring the cost of adding a passive Si interposer, TSI avoids the issues faced by TSV based 3D configuration related to the high-temperature gradients because of poor thermal distribution, difficult IO planning, large keep-out areas and reliable manufacturing [10,13,15,16]. When compared with traditional backplane through-PCB interconnections which span lengths of few inches (>25 cm), TSI interconnects are much shorter (few mm) in length [2], which is one of the main reasons for their enhanced performance. For example, at 5 Gbps a 25-cm-long PCB track suffers from approximately 20-dB additional channel l...

Summary A configurable full‐duplex low‐voltage differential signaling transceiver is presented, which can be configured to operate either for smaller differential channels (a few inches of striplines) or for longer channels (10 m of twisted pair cables). The configurability is embedded in the form of functionalities like pre‐emphasis, equalization, and slew rate control within the transceiver. The transmitter employs a hybrid voltage–current‐mode driver, which due to replica action, achieves a high‐impedance current‐mode signal dispatch and at the same time provides a matched impedance at the near end for improved intersymbol interference. The transmitter achieves slew rate control through a band‐limited pre‐driver, while the pre‐emphasis is achieved through a capacitive feed‐forward. The receiver employs a large‐input common‐mode first stage enclosed in a common‐mode control loop that enables its first stage to also act like a domain shifter (VDDIO‐to‐VDDCORE) reducing the overall power consumption. The equalization in the receiver is implemented by using carefully sized active inductive loads inside the receiver. The transceiver is designed and fabricated in 150‐nm complementary metal–oxide–semiconductor, sharing the space with a larger die, occupying an area of 400 × 400μm. The measurement results demonstrate that the transceiver is operating at 2 Gbps both for a 4‐in microstrip and a 10‐m twisted pair CAT6 cable with 30 and 180 ps of total jitter, respectively. The built‐in impedance calibrator minimizes the spread in the on‐die termination at the near end provided by the transmitter‐minimizing bit error rate across process, voltage, and temperature corners. The transmitter consumes a total power of 17 mW operating at 2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps. Copyright © 2016 John Wiley & Sons, Ltd.