Low voltage swing logic circuits for a Pentium® 4 processor integer core

Deleganes, D.J.; Barany, Micah; Geannopoulos, G.; Kreitzer, K.C.; Singh, A.P.; Wijeratne, S.

doi:10.1145/996566.996751

Cited by 12 publications

(9 citation statements)

References 3 publications

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“…1) [6], [7]. The complementary logic and the differential signals lead to enhanced signal reliability as the differential sense amplifier rejects common noises.…”

Section: Intel Lvs Logicmentioning

confidence: 99%

Intel LVS logic in CNT technology

Zeng

Liu

Cao

et al. 2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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In this paper, we systematically evaluate combinational logic families for CNT technology implementation for a variety of logic families, signal transition times, and transistor parameters. We compare CMOS static logic, and Intel LVS logic in CNT and silicon technologies by SPICE simulation based on Predictive Technology Model and Stanford compact CNFET models. We observe that CMOS static logic in CNT technology achieves limited (e.g., 3.44×) performance improvement and (e.g., 3.83×) power consumption reduction, while Intel LVS logic achieves more significant performance improvement and ordersof-magnitude of power consumption reduction. Intel LVS logic achieves an average of 4.02× performance improvement and 1137.64× power consumption reduction compared with CMOS static logic in silicon for the same combinational logic functions and input signals, and enhanced reliability, making it an ideal combinational logic circuit paradigm in CNT technology.

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“…1) [6], [7]. The complementary logic and the differential signals lead to enhanced signal reliability as the differential sense amplifier rejects common noises.…”

Section: Intel Lvs Logicmentioning

confidence: 99%

Intel LVS logic in CNT technology

Zeng

Liu

Cao

et al. 2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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“…As the LVS signals have to flow in the circuit differentially [1], we use two complement branches of this chain in the whole circuit. The building block of our carry-generate circuit is shown in the bubble (i = 0 in this building block) in Fig.…”

Section: Adder Structurementioning

confidence: 99%

“…In the worst case situation where carry has to propagate from carry-in input to the bit 27, it has to pass through 9 pass-transistors in the carry-generate circuit to reach the 8th sum-generate circuit. For the LVS carry skip structure [1] it is mentioned that the LVS signal should not propagate through more than 6 pass-transistors to keep its strength, however, in comparison as there are no pass-transistor-based XOR gates after each pass-transistor in our carrygenerate tree (as the sum signals generate separately), the carry signal keeps its strength at the worst case too. To keep the signal strength, the input carry of the whole circuit and its complement are applied to the first carry-generate stage with transmission gates controlled by P 0 signal (Fig.…”

Section: Carry-generate Circuitmentioning

confidence: 99%

“…In the output nodes of the circuit which are sum and 31st carry outputs, sense amplifiers are used to amplify differential small signals to the standard levels of zero and one [1]. Propagate, generate, and kill signals are produced with static logics, while two-input and four-input AND gates are implemented with dynamic logic.…”

Section: Sum-generate Circuitmentioning

confidence: 99%

“…Low-voltage-swing topologies [1,2] and carrylookahead structures with sparse tree carry-generate circuits [3,4] are two important techniques used in the latest high speed adders.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

15GHz low-voltage-swing carry-lookahead adder

Kashfi

Agah

Fakhraie

et al. 2007

IEICE Electron. Express

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High performance current-mode differential logic

Zhang¹,

Liu²,

Zhu³

et al. 2008

2008 Asia and South Pacific Design Automation Conference

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This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage swing (LVS) logic, CMDL uses a shunt resistor at the differential output to obtain constant low swing signal without the need to reset low. Furthermore, conditional shunt transistors are used for the internal nodes to prevent high-voltage swing, thus entirely eliminate the power-hungry clocked reset network in LVS circuits. We show that the CMDL is suitable for high-end microprocessor integer core by providing three datapath modules implemented in CMDL. Our simulation results indicate that, operating at comparable speed with LVS logic, CMDL circuits can achieve up to 50% reduction of delay-power product compared to CMOS logic and LVS logic. In addition, CMDL reduces the power consumption of LVS by up to 40%.

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Low voltage swing logic circuits for a Pentium® 4 processor integer core

Abstract: The Pentium® 4 processor architecture uses a 2x frequency core clock[1] to implement low latency integer ops. Low Voltage Swing logic circuits implemented in 90nm technology[2] meet the frequency demands of a third generation integer-core design.

Cited by 12 publications

References 3 publications

Intel LVS logic in CNT technology

Intel LVS logic in CNT technology

15GHz low-voltage-swing carry-lookahead adder

High performance current-mode differential logic

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