Lower power, lower delay design scheme for CMOS tapered buffers

Shebaita, Ahmed; Ismail, Yehea

doi:10.1109/idt.2009.5404147

Cited by 1 publication

(2 citation statements)

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“…It is observed that increasing the threshold voltage between 0.2 V DD and 0.4 V DD gives the highest reduction in power with a minimal penalty in delay. Thereafter, the propagation delay increases quickly as V th is increased beyond 0.4 V DD and a high penalty in terms of speed has to be paid [4]. It is necessary to mention here that there is another incentive in not allowing the threshold voltage to increase beyond 0.4 V DD which is that the threshold voltage value should be less than the switching threshold V M = (0.5V DD ).…”

Section: Power and Delay Optimizationmentioning

confidence: 99%

“…while working in nano scale technology the total power dissipation of clock drivers, which generally have CMOS inverters, is quite large and have 30 to 50% share only of leakage current and short circuit current [1,2]. To solve this problem of high power dissipation, a design scheme has been proposed, which not only minimizes short circuit power, and leakage power but also optimizes propagation delay [3,4]. So our work presents a CMOS taper buffer design which considers the power dissipation as dominant cost function.…”

Section: Introductionmentioning

confidence: 99%

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"Low Power, Delay Optimised Buffer Design using 70nm CMOS Technology"

Sharma¹,

Mehra²

2011

IJCA

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This paper addresses the issues of power dissipation and propagation delay in CMOS buffers driving large capacitive loads and proposes a CMOS buffer design for improving power dissipation at optimized propagation delay. The reduction in power dissipation is achieved by minimizing short circuit power and subthreshold leakage power which is predominant when supply voltage (V DD ) and threshold voltage (V th ) are scaled for low voltage applications in deep submicron (DSM) region. The proposed buffer has been designed and simulated using Tanner SPICE tool in 70 nm VLSI technology node. The results show that modified taper buffer design provides 15% reduction in power dissipation at same value of propagation delay when compared with conventional design.

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Section: Power and Delay Optimizationmentioning

confidence: 99%