Abstract-This paper presents a framework for fast and accurate static timing analysis considering coupling. With technology scaling to smaller dimensions, the impact of coupling induced delay variations can no longer be ignored. Timing analysis considering coupling is iterative, and can have considerably larger run-times than a single pass approach. We propose a novel and accurate coupling delay model, and present techniques to increase the convergence rate of timing analysis when complex coupling models are employed. Experimental results obtained for the ISCAS benchmarks show promising accuracy improvements using our coupling model while an efficient iteration scheme shows significant speedup (up to 62.1%) in comparison to traditional approaches.

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Timing analysis is a key component of any integrated circuit (IC) chip design-closure flow, and is employed at various stages of the flow including pre/post-route timing optimization and timing signoff. While accurate timing analysis is important, the run-time of the analysis is equally critical with growing chip design sizes and complexity (for example, increasing number of clocks domains, voltage islands, etc.). In addition, the increasing significance of variability in the chip manufacturing process as well as environmental variability necessitates use of variation aware techniques (e.g., statistical, multi-corner) for chip timing analysis which significantly impacts the analysis run-time.The aim of the TAU 2013 variation aware timing contest is to seek novel ideas for fast variation aware timing analysis, by means of the following: (a) increase awareness of variation aware timing analysis and provide insight into some challenging aspects of the analysis, (b) encourage novel parallelization techniques (including multi-threading) for timing analysis, and (c) facilitate creation of a publicly available variation aware timing analysis framework and benchmarks to further advance research in this area.

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