LRU-SEQ: a novel replacement policy for transition energy reduction in instruction caches

A Replacement Policy to Save Energy for Data Cache

“…bank transitions to effect leakage power savings. Common circuit level static power optimizations are: 1) Gated-V DD : Deactivate non-essential parts of the circuit by gating the source voltage, 2) Multiple V T (dual V T ) & Dynamic V T : Changing the threshold voltage of the circuit to control the switching of the transistors, 3) Biasing bit-lines for low leakage and fast wakeup times, and 4) Silicon over Insulator (SOI) implementations also reduce leakage power by reducing the charge leakage through bulk [3][4] [5].…”

“…A replacement policy that has successfully exploited a pattern of accesses in instruction caches is the LRU-SEQ replacement policy, due to the way it "constrains sequential fills to the previously accessed bank", thereby avoiding unnecessary replacement, reducing energy consumed and improving miss rates [3]. LRU-SEQ policy is unique since it proposes architectural level cache optimizations to exploit circuit level phenomenon e.g.…”