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This paper presents a new instruction cache scheme: the TAC (Thrashing-Avoidance Cache). A 2-way TAC scheme employs 2-way banks and XOR mapping functions. The main function of the TAC is to place a group of instructions separated by a call instruction into a bank according to the Bank Selection Logic (BSL) and Bank-originated Pseudo-LRU replacement policies (BoPLRU). After the BSL initially selects a bank on an instruction cache miss, the BoPLRU will determine the final bank for updating a cache line as a correction mechanism. These two mechanisms can guarantee that recent groups of instructions exist in each bank safely. We have developed a simulation program, TACSim, by using Shade and Spixtools, provided by SUN Microsystems, on an ultra SPARC/10 processor. Our experimental results show that 2-way TAC schemes reduce conflict misses more effectively than 2-way skewed-associative caches in both C (17% improvement) and C++ (30% improvement) programs on L1 caches.

hstructlon fetch speeds are Improved by uslng cache schemes that are based on dynamic flow OP program inslructlom VarlableSlzed Block Cache (VSBC) Is a oew instrucllon scheme that slores bask code blocks and their boundarks as traces. Current trace-or block-based cache schemes usually have some imtructlons stored repeatedly; this redundancy Is ellmlonried In VSBC. The sludles done so far, in slngle-and multl-threaded envtronments, have shown . improvements in trace m l s rate. Other aspects of VSBC performance such as trace leqgth and latency a r e being studied.1. k4TRODUCnON & RELATED WORK Processor speeds in the past decades have risen at a rate much higher than the memory speed. Placing fast caches close to the processor reduces memory latency by storing frequently or recently accessed data and instructions [1],[2]. Rotenberg, er al [31,[4],[5]presented itace cache (TC) that stored instructions as they executed. TC's excessive switching from irate build mode to rruce urilization mode had a negative effect on TC-based processor system's IPC. Black, er al [6] also used basic code blocks as units of instruction storage in cache and called this scheme block cache. Drawbacks of this scheme were block cache fragmentation and storage of same code blocks in multiple places. Jourdan, er d [ 7 ] came up with emended block (XB) cache in which the instructions (uops) were stored in reverse sequence; this gave them the ability to extend any existing XB's. They reported reduced fragmentation and a bandwidth similar to trace cache. OVERVIEW OF THIS PAPERIn this paper, we present variable-sized bbck cache (VSBC) architecture. VSBC addresses the issue of instruction overlap among traces that occur frequently in conventional trace cache scheme'. VSBC enables storage of code blocks without the replicated block storage structures as required in block cache 161. VSBC's implementation in hardware is only sIightly more complex than trace cache but is much simpler than block cache.The focus of this paper is VSBC's own performance and not that of a complete processor system. For the initial studies, we ' In a sim-cache [8][9] based TC model that ran 100 million instructions, we measured ihe instruction overlap among taces for SpecInQOOO benchmarks.We saw the overlap to be 25.1% for crafty benchmark 38.5% for mcfand 79.5% for bzip. chose rruce miss rate as the perfoknce metric. VSBC-ST refers to VSBC in single-threaded environment whereas VSBC-MT m a n s VSBC in multi-threaded environment. VARIABLE BLOCK SEED CACHE -ARCHITECTURE A. VSBC -OverviewBasic code blocks are constructed dynamically, i.e., while the program is executing. Beginning of a basic block is called its block head. Block head is also the destination of a control transfer instruction such as conditionaYunconditional jump, return and call. End of a basic block called the block ~i l marked by a control transfer instruction. Basic blocks have no size limitations other than the cache capacity. VSBC stores code in program execuvion order. Each trace in VSBC is made up of m...

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